[SI-LIST] Re: Tightly coupled VS loosely coupled diff pairs
- From: MikonCons@xxxxxxx
- To: si-list@xxxxxxxxxxxxx
- Date: Wed, 12 Sep 2001 16:37:28 EDT
In a message dated 9/10/01 6:14:58 PM Pacific Daylight Time,
cheard@xxxxxxxxxx writes:
> Can you comment on the effect on pcb thickness and therefore plated through
> hole capacitance of running broadside coupled? Thickness certainly
> increases which drives capacitance up which can dominate connector Zo
> matching. Is this more significant a problem than localized differences in
> Er and glass/resin? There are some companies talking about "counterboring"
> plated through holes to virtually eliminate capacitance in order to get into
>
There are two subjects here, but please understand that when dealing with
higher and higher clock and edge rates, ALL SI considerations become
"significant." Therefore, all facets should be considered simultaneously,
and, like so many other natural phenomena, some effects cancel or balance
others. Our task is to properly meld these effects with judgement to yield an
optimum design for the intended application.
For broadside-coupled (BC) pairs, each specific board may be different. The
number of layers, as well as the board thickness has an impact on the
effective impedance and the effective length of each of the traces, as
measured by time-of-flight of the signal component on each trace. Howard
Johnson provided a good description of the considerations to be aware of some
many months past (you might do a search of the archives). One way or another,
the added signal path length of the trace most deeply buried needs to be
accommodated. And, YES, the impact of the added capacitance of the longer
vias associated with the thicker board must also be accommodated. Note that
the impact of this added capacitance is stronger for edge-coupled (EC) pairs
than BC pairs, and can often be 20 to 30 Ohms for a 100-Ohm pair. Much of the
impact on EC pairs can be mitigated by transitioning the maximum distance
through the connector and package pin through-holes; i.e., the through-hole
inductance can be balanced with the capacitance to approach a 50-Ohm
single-ended trace.
To date, I've never had to use counter-boring to achieve reliable
performance; however, the technical validity of the approach has been
verified and reported in papers by AMP (check their web site). The cost also
has (so far) kept me from recommending that approach to my clients. When
performance demands, and cost is not dominant, I would probably consider
sequential lamination buildup of the board to achieve shorter copper
penetration into the board for the high-speed traces (as opposed to the
counter bore approach). If deemed necessary, this approach should be worked
directly with your board fabricator to obtain a technically adequate solution
at the lowest cost.
Mike
Michael L. Conn
Owner/Principal Consultant
Mikon Consulting
(408)727-5697
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