[SI-LIST] Re: Thoughts on via sharing
- From: Ivor Bowden <ivor@xxxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Fri, 15 Apr 2005 12:00:35 -0700
One advantage of via sharing for power is that it minimizes the relief
area on the the other power planes, more power vias = less power plane!
I think the reasons for not via sharing have more to do with series
inductance to the power pins rather than static load current.
Ivor
on 4/15/2005 6:45 AM Santangelo, Steven wrote:
>Hi,
>
>I know in general that via sharing, specifically on power and gnd pins, =
>is not a desirable thing. However, there are cases where it becomes =
>very difficult not so do some sharing. For example, when doing a design =
>with back to back devices, it becomes nearly impossible not to share =
>some vias. In some cases it can be avoided by extending the breakout =
>etch further from the device, but this would appear worse than sharing a =
>via. So my question is, if you have a case where you have to do some =
>sharing, are there any rules of thumb that can be followed to minimize =
>the risk? For example, # of pins sharing a via versus load current, =
>size of the via versus size of the etch and number of connections =
>feeding it, etc.
>
>Thanks
>
>Steve
>=20
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