[SI-LIST] Re: Thoughts on via sharing
- From: steve weir <weirsi@xxxxxxxxxx>
- To: SSantangelo@xxxxxxxxxxxx, <si-list@xxxxxxxxxxxxx>
- Date: Fri, 15 Apr 2005 11:52:56 -0700
Steven, consider what sharing does, and then you can decide where it is and
is not acceptable. For a plane pair sourcing devices on both sides of the
board, a through via can be considered two separate vias that touch at the
plane. However for a via sourcing two loads on the same surface, the
di/dt*L noise of each load adds. It's not the most desirable thing in the
world, but whether it is a serious problem or not comes down to numbers.
You can: derive, or look-up the partial inductance for a given via pair to
get an idea of the attachment impedance. You can obtain these numbers from
Dr. Johnson's web site, www.sigcon.com or from my papers on the Teraspeed
web site, www.teraspeed.com. If you don't let the attachment inductance
get too out of hand then you can make up for it with the planes, and / or
bypass caps. However, if you take it too far, you will exceed your noise
budget no matter what you do with the planes or capacitors.
Steve
At 09:45 AM 4/15/2005 -0400, Santangelo, Steven wrote:
>Hi,
>
>I know in general that via sharing, specifically on power and gnd pins, =
>is not a desirable thing. However, there are cases where it becomes =
>very difficult not so do some sharing. For example, when doing a design =
>with back to back devices, it becomes nearly impossible not to share =
>some vias. In some cases it can be avoided by extending the breakout =
>etch further from the device, but this would appear worse than sharing a =
>via. So my question is, if you have a case where you have to do some =
>sharing, are there any rules of thumb that can be followed to minimize =
>the risk? For example, # of pins sharing a via versus load current, =
>size of the via versus size of the etch and number of connections =
>feeding it, etc.
>
>Thanks
>
>Steve
>=20
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