Copper utilization runs from a few percent to about 40%.
I fill unused space on inner layers only when I want to create inner layer
capacitance without needing to add any more plane layers, otherwise, no.
I've never seen a case where copper balancing was necessary. I've heard it
talked about, but not seen a case where it was needed.
I'm not sure what the +/- 10% refers to. Can you clarify that?
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On ;
Behalf Of Christian D'Souza
Sent: Friday, November 17, 2017 2:05 PM
To: leeritchey@xxxxxxxxxxxxx
Cc: Scott McMorrow <Scott@xxxxxxxxxxxxx>; Havermann, Gert
<Gert.Havermann@xxxxxxxxxxx>; CurtM@xxxxxxxxxxx; w.maichen@xxxxxxx;
riaziabe@xxxxxxxxx; Alexander Ippich <alexander.ippich@xxxxxxxxxxxxxxx>;
si-list <si-list@xxxxxxxxxxxxx>; si-list-bounce@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Thieving Article
Lee.
I do have a few questions if I may.
1. What is the Cu % utilization of the inner layers in most of the designs you
consult for or review?
2. Do you recommend or do plane fills on inner signal layers?
3. If yes to 2., in what way is this not "cu balancing"?
4. Do you believe +/- 10% is adequate for complex RF interfaces on a mixed
signal pcb?
Best regards,
Christian
On Fri, Nov 17, 2017 at 12:38 PM, Lee Ritchey <leeritchey@xxxxxxxxxxxxx>
wrote:
I have not run into the need to do copper balancing on inner layers.
Long ago, when we put several PCB stacks into a press opening we would
run into uneven thickness on finished PCBs. This problem was solved
by putting "call plates" between each PCB stackup. This results in
much more uniform thickness and solved the copper balance problem. As
to impedance variations due to sparse vs dense routing, my experience
is that this will stay well within the =/- 10% bounds we normally put
on our fabricators, so I see no need to do any copper balancing.
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Scott McMorrow
Sent: Friday, November 17, 2017 5:32 AM
To: Havermann, Gert <Gert.Havermann@xxxxxxxxxxx>;
leeritchey@xxxxxxxxxxxxx; CurtM@xxxxxxxxxxx; w.maichen@xxxxxxx;
riaziabe@xxxxxxxxx; alexander.ippich@xxxxxxxxxxxxxxx
Cc: 'si-list' <si-list@xxxxxxxxxxxxx>; si-list-bounce@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Thieving Article
Thieving is still the name that fabricators use, but on a sparse board
I like to think of it as copper balance (like we do in packages) that
is used to create a more uniform laminate press. It makes quite a
difference in impedance control when copper traces are sparse.
Scott McMorrow, CTO Signal Integrity Group Samtec Office 401-284-1827
|
+1-800-726-8329 www.samtec.com
-----Original Message-----
From: Havermann, Gert [mailto:Gert.Havermann@xxxxxxxxxxx]
Sent: Friday, November 17, 2017 8:29 AM
To: Scott McMorrow <Scott@xxxxxxxxxxxxx>; leeritchey@xxxxxxxxxxxxx;
CurtM@xxxxxxxxxxx; w.maichen@xxxxxxx; riaziabe@xxxxxxxxx;
alexander.ippich@xxxxxxxxxxxxxxx
Cc: 'si-list' <si-list@xxxxxxxxxxxxx>; si-list-bounce@xxxxxxxxxxxxx
Subject: RE: [SI-LIST] Re: Thieving Article
Scott,
I didn't know that there was a special term when you add copper to the
outer or inner Layer, I only knew about the different purpose, but I
thought it is called the same.
So for me (and several of our PCB manufacturers) thieving was simply
adding the dots or squares to whatever Layer, why does the name make a
difference? Do you know where the Term "Thieving" is based on?
----------------------------------------
HARTING AG & Co. KG, Postfach 11 33, 32325 Espelkamp;
Marienwerderstraße 3, 32339 Espelkamp Generalbevollmächtigte
Gesellschafterin: Dipl.-Hdl.
Margrit Harting Persönlich haftende Gesellschafterin: HARTING WiMa AG
(Luxemburg) & Co. KG; Amtsgericht Bad Oeynhausen; HRA 8259;
persönlich haftende Gesellschafterin: HARTING Führungs AG (Registre
de Commerce et des Sociétés Luxembourg), B 170749, Luxemburg
Vorstand: Dipl.-Kfm. Philip F. W. Harting (Vorsitzender), Dipl.-Kffr.
Maresa W. M. Harting-Hertz, Dipl.-Kfm. Dr.-Ing. E. h. Dietmar Harting, Dr.
rer. nat. Frank Brode, Dipl.-Ing. (FH), Dipl.-Wirtsch.-Ing. (FH)
Andreas Conrad, Dr. iur. Michael Pütz; Sitz der Gesellschaft:
Espelkamp; Amtsgericht Bad Oeynhausen; HRA 9021; UST-ld Nr.
DE812136745
-----Original Message-----
From: Scott McMorrow [mailto:Scott@xxxxxxxxxxxxx]
Sent: Friday, November 17, 2017 1:49 PM
To: Havermann, Gert <Gert.Havermann@xxxxxxxxxxx>;
leeritchey@xxxxxxxxxxxxx; CurtM@xxxxxxxxxxx; w.maichen@xxxxxxx;
riaziabe@xxxxxxxxx; alexander.ippich@xxxxxxxxxxxxxxx
Cc: 'si-list' <si-list@xxxxxxxxxxxxx>; si-list-bounce@xxxxxxxxxxxxx
Subject: RE: [SI-LIST] Re: Thieving Article
In that case it's not for Thieving, but for copper balance to keep the
layers flat. Since we require ground stitch vias on our test boards
and backplanes, we have them perform a dual-purpose and place
oversized square pads on them.
Scott McMorrow, CTO Signal Integrity Group Samtec Office 401-284-1827
|
+1-800-726-8329 www.samtec.com
-----Original Message-----
From: Havermann, Gert [mailto:Gert.Havermann@xxxxxxxxxxx]
Sent: Friday, November 17, 2017 2:52 AM
To: leeritchey@xxxxxxxxxxxxx; CurtM@xxxxxxxxxxx; Scott McMorrow <
Scott@xxxxxxxxxxxxx>; w.maichen@xxxxxxx; riaziabe@xxxxxxxxx;
alexander.ippich@xxxxxxxxxxxxxxx
Cc: 'si-list' <si-list@xxxxxxxxxxxxx>; si-list-bounce@xxxxxxxxxxxxx
Subject: RE: [SI-LIST] Re: Thieving Article
Lee,
we do it on every second Backplane Design because we have to
(production yield). And the Backplane PCB supplier really always asks
for thieving on inner and outer layers. And as I said, it's mainly a
backplane issue where you have Layers with less than 2% copper fill.
BR
Gert
----------------------------------------
HARTING AG & Co. KG, Postfach 11 33, 32325 Espelkamp;
Marienwerderstraße 3, 32339 Espelkamp Generalbevollmächtigte
Gesellschafterin: Dipl.-Hdl.
Margrit Harting Persönlich haftende Gesellschafterin: HARTING WiMa AG
(Luxemburg) & Co. KG; Amtsgericht Bad Oeynhausen; HRA 8259;
persönlich haftende Gesellschafterin: HARTING Führungs AG (Registre
de Commerce et des Sociétés Luxembourg), B 170749, Luxemburg
Vorstand: Dipl.-Kfm. Philip F. W. Harting (Vorsitzender), Dipl.-Kffr.
Maresa W. M. Harting-Hertz, Dipl.-Kfm. Dr.-Ing. E. h. Dietmar Harting, Dr.
rer. nat. Frank Brode, Dipl.-Ing. (FH), Dipl.-Wirtsch.-Ing. (FH)
Andreas Conrad, Dr. iur. Michael Pütz; Sitz der Gesellschaft:
Espelkamp; Amtsgericht Bad Oeynhausen; HRA 9021; UST-ld Nr.
DE812136745
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Lee Ritchey
Sent: Thursday, November 16, 2017 6:58 PM
To: CurtM@xxxxxxxxxxx; Scott@xxxxxxxxxxxxx; w.maichen@xxxxxxx;
riaziabe@xxxxxxxxx; alexander.ippich@xxxxxxxxxxxxxxx
Cc: 'si-list' <si-list@xxxxxxxxxxxxx>; si-list-bounce@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Thieving Article
I have not seen thieving added to inner layers.
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Curt McNamara
Sent: Thursday, November 16, 2017 8:36 AM
To: Scott@xxxxxxxxxxxxx; w.maichen@xxxxxxx; riaziabe@xxxxxxxxx;
alexander.ippich@xxxxxxxxxxxxxxx
Cc: leeritchey@xxxxxxxxxxxxx; si-list <si-list@xxxxxxxxxxxxx>;
si-list-bounce@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Thieving Article
Great points. Thieving is commonly added (to both external and
internal
layers) to increase yield.
Here is an IPC article that mentions this along with other best
practice recommendations.
Curt
http://ipc-rtp.org/past_files/A-Z__2013_IPC_RTP.pdf
________________________________
From: si-list-bounce@xxxxxxxxxxxxx <si-list-bounce@xxxxxxxxxxxxx> on
behalf of Alexander Ippich <alexander.ippich@xxxxxxxxxxxxxxx>
Sent: Thursday, November 16, 2017 10:27:19 AM
To: Scott@xxxxxxxxxxxxx; w.maichen@xxxxxxx; riaziabe@xxxxxxxxx
Cc: leeritchey@xxxxxxxxxxxxx; si-list; si-list-bounce@xxxxxxxxxxxxx;
Alexander Ippich
Subject: [SI-LIST] Re: Thieving Article
If I would have to get down to these fractions of cents, I would side
with Scott. However, the big influence is regarding manufacturability / yield.
That's why thieving is added.
Don't put it on, and you may find that the outerlayer design is to
irregular to get the plating right (overplating isolated features),
causing scrap.
Similar with thieving on innerlayers, this time protecting isolated
features from too aggressive etching.
So my point of view would be, that allowing your PCB supplier to add
thieving (don't forget to give them rules, as Lee has mentioned) is
going to reduce overall PCB cost. Probably not in the short run (cost
models are most likely not that detailed), but it can have an impact
on yield and then on your ability to negotiate cost reductions.
Best regards,
alex
------------------------------------------------------------
----------------
------------------------------------------------------------
Alexander Ippich
Technical Director, Signal Integrity & Advanced Technology OEM
Marketing Europe
e-mail: alexander.ippich@xxxxxxxxxxxxxxx
web: www.isola-group.com<http://www.isola-group.com>
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Scott McMorrow
Sent: Thursday, November 16, 2017 4:43 PM
To: w.maichen@xxxxxxx; riaziabe@xxxxxxxxx
Cc: leeritchey@xxxxxxxxxxxxx; si-list; si-list-bounce@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Thieving Article
On the other side, there is less copper available for recycling. I'd
guess it is a push in terms of cost.
Scott McMorrow, CTO Signal Integrity Group Samtec Office 401-284-1827
|
+1-800-726-8329 www.samtec.com<http://www.samtec.com>
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Wolfgang Maichen
Sent: Thursday, November 16, 2017 10:38 AM
To: riaziabe@xxxxxxxxx
Cc: leeritchey@xxxxxxxxxxxxx; si-list <si-list@xxxxxxxxxxxxx>;
si-list-bounce@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Thieving Article
My guess would be that if anything it will result in slightly LOWER
manufacturing cost because you etch away less copper, thus consume
less etchant.
From:Abe Riazi <riaziabe@xxxxxxxxx>
To:leeritchey@xxxxxxxxxxxxx
Cc:si-list <si-list@xxxxxxxxxxxxx>
Date:16.11.2017 16:35
Subject:[SI-LIST] Re: Thieving Article Sent
by:si-list-bounce@xxxxxxxxxxxxx
Hi Lee,
I reviewed your interesting article entitled "Thieving in Printed
Circuit Boards", and have two question:
1. Does thieving has any effect on "thermal" performance of the board ?
2. Does it increase the PCB manufacturing cost?
Thank you in advance for your response.
Abe
On Wed, Nov 15, 2017 at 3:13 PM, Lee Ritchey
<leeritchey@xxxxxxxxxxxxx>
wrote:
I am often asked what the extra small dots are on the outer layersmany
of
dense PCBs. It is called thieving and I wrote an article explainingwhat
it is and why it is used. You can download a copy from our web site<http://www.speedingedge.com> .
www.speedingedge.com<http://www.speedingedge.com>
Lee Ritchey
Speeding Edge
P.O. Box 817
Bodega Bay, CA
94923
408-781-0253
I just used the energy it takes
To get mad and wrote some blues.
Count Basie
Or:
Worry is like a rocking chair,
It keeps you busy but.
It doesn't get you anywhere.
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