Hello Aubrey,
stacking microvias indeed require reliable and accurate via filling to
ensure good contact from one via to the next on top of it. That's why in
the past - when this was not a given, manufacturing processes less mature -
people resorted to staggering vias instead, i.e. horizontally offsetting
each via from the previous one. This way one could leave the vias unfilled
(or partially filled) because the next via would hit a pad adjacent to it.
Of course there is a price to pay - increased space requirement (via +
pad) / reduced routing area for the rest of the structures. In the meantime
PCB manfacturing has made quite some progress so in my experience stacked
vias are not often used anymore in high-end fabrication (though nobody will
prevent you designing staggered vias if you want to) - after all, the main
reason for HDI (high-density interconnect) builds with small line widths
and small vias is to maximize routing density (or minimize product size).
Best regards,
Wolfgang
From: Aubrey Sparkman <asparky@xxxxxxxxxxxxxxxxxxxxxxxx>
To: w.maichen@xxxxxxx
Cc: Alexander Ippich <alexander.ippich@xxxxxxxxxxxxxxx>,
dmarc-noreply@xxxxxxxxxxxxx, si-list@xxxxxxxxxxxxx
Date: 16.10.2017 12:13
Subject: Re: [SI-LIST] Re: Stacked microvia on high speed diff layer
transitions
Wolfgang,
I have heard that staggering the vias enhances reliability.
Sent from my iPhone
On Oct 16, 2017, at 2:43 AM, Wolfgang Maichen <w.maichen@xxxxxxx> wrote:considerations
Hello Alex,
point taken, although I would tend to argue that such yield
are a general consideration for sequential build-ups, not somethingoff
specifically related to stacked vias. If layer-to-layer registration is
for any layer, it will impact your yield for HDI boards, no matter if youthe
have stacked vias or not.
For high-end boards there actually is quite some testing after each
lamination step - x-ray for registration, optical vision inspection of
surfaces, and possibly electrical open/short testing - to minimize thestages.
probability of bad subassemblies making it into further processing
Best regards,
Wolfgang
From: Alexander Ippich <alexander.ippich@xxxxxxxxxxxxxxx>
To: w.maichen@xxxxxxx, dmarc-noreply@xxxxxxxxxxxxx
Cc: si-list@xxxxxxxxxxxxx, Alexander Ippich
<alexander.ippich@xxxxxxxxxxxxxxx>
Date: 16.10.2017 09:02
Subject: RE: [SI-LIST] Re: Stacked microvia on high speed diff layer
transitions
Wolfgang, Ed,
I need to somewhat disagree. Ok, there is no *THEORETICAL* limit to the
number of microvias that can be stacked. But for sure there is an
economical limit.
This is a sequential process. And unfortunately, the intermediate steps /
sub-assemblies can not be fully tested. So a defect part may be processed
further.
Just for the sake of demonstration, let's assume that each sub-assembly
can be manufactured with a yield of 95%:
