Hello Alex,
point taken, although I would tend to argue that such yield considerations
are a general consideration for sequential build-ups, not something
specifically related to stacked vias. If layer-to-layer registration is off
for any layer, it will impact your yield for HDI boards, no matter if you
have stacked vias or not.
For high-end boards there actually is quite some testing after each
lamination step - x-ray for registration, optical vision inspection of the
surfaces, and possibly electrical open/short testing - to minimize the
probability of bad subassemblies making it into further processing stages.
Best regards,
Wolfgang
From: Alexander Ippich <alexander.ippich@xxxxxxxxxxxxxxx>
To: w.maichen@xxxxxxx, dmarc-noreply@xxxxxxxxxxxxx
Cc: si-list@xxxxxxxxxxxxx, Alexander Ippich
<alexander.ippich@xxxxxxxxxxxxxxx>
Date: 16.10.2017 09:02
Subject: RE: [SI-LIST] Re: Stacked microvia on high speed diff layer
transitions
Wolfgang, Ed,
I need to somewhat disagree. Ok, there is no *THEORETICAL* limit to the
number of microvias that can be stacked. But for sure there is an
economical limit.
This is a sequential process. And unfortunately, the intermediate steps /
sub-assemblies can not be fully tested. So a defect part may be processed
further.
Just for the sake of demonstration, let's assume that each sub-assembly
can be manufactured with a yield of 95%:
2-layer -- final yield 95%
4-layer -- final yield = 95% * 95% = 90.25%
6-layer -- final yield = 'yield of 4-layer' * 95% = 85.7%
8-layer -- final yield = 'yield of 6-layer' * 95% = 81.5%
...
I guess, this makes my point pretty clear. The more often that you go
through this sequential process, the worse the final product yield. In
most applications, 5 or 6 relamination cycles will be the maximum that
still has a decent output. For 6 relams, yield would in this example
already drop to 73.5%.
Best regards,
alex
--------------------------------------------------------------------------
--------------------------------------------------------------
Alexander Ippich
Technical Director, Signal Integrity & Advanced Technology
OEM Marketing Europe
e-mail: alexander.ippich@xxxxxxxxxxxxxxx
web: www.isola-group.com
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Wolfgang Maichen
Sent: Monday, October 16, 2017 8:51 AM
To: dmarc-noreply@xxxxxxxxxxxxx
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Stacked microvia on high speed diff layer
transitions
Hello Ed,
there is no limit as to how many microvias can be stacked. On
state-of-the-art HDI (high-density interconnect) multilayer boards you can
have vias stacked all across the board through all layers (i.e. avoiding
the aspect ratio limitation for mechanical drilling determined by the
total board thickness).
Since using microvias it is easy to have the via only crossing the layeras
of interest (i.e. no unwanted stubs at either end), they can provide
excellent high-frequency performance. Of course the other important factor
is the presence of a suitable return path, i.e. one or more return via at
proper distance. The goal here is to have via capacitance and via/return
via path inductance to balance out to the desired line impedance (e.g. 50
Ohm).
Best Regards,
Wolfgang
From: "Eduard Pulaha" <dmarc-noreply@xxxxxxxxxxxxx> (Redacted sender
"epulaha" for DMARC)
To: "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
Date: 15.10.2017 03:35
Subject: [SI-LIST] Stacked microvia on high speed diff layer
transitions
Sent by: si-list-bounce@xxxxxxxxxxxxx
Hello,
Breakouts of BGAs with over 1000 bumps are driving the usage of stacked
microvias in our pcb stackups. Wanted to know if their usage is
recommended for high speed diff transitions and whether there is a limit
in terms of how many can be stacked (2, 3 or beyond) and the effect on
signal integrity.
Thanks,Ed
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