Wolfgang,
I have heard that staggering the vias enhances reliability.
Sent from my iPhone
On Oct 16, 2017, at 2:43 AM, Wolfgang Maichen <w.maichen@xxxxxxx> wrote:------------------------------------------------------------------
Hello Alex,
point taken, although I would tend to argue that such yield considerations
are a general consideration for sequential build-ups, not something
specifically related to stacked vias. If layer-to-layer registration is off
for any layer, it will impact your yield for HDI boards, no matter if you
have stacked vias or not.
For high-end boards there actually is quite some testing after each
lamination step - x-ray for registration, optical vision inspection of the
surfaces, and possibly electrical open/short testing - to minimize the
probability of bad subassemblies making it into further processing stages.
Best regards,
Wolfgang
From: Alexander Ippich <alexander.ippich@xxxxxxxxxxxxxxx>
To: w.maichen@xxxxxxx, dmarc-noreply@xxxxxxxxxxxxx
Cc: si-list@xxxxxxxxxxxxx, Alexander Ippich
<alexander.ippich@xxxxxxxxxxxxxxx>
Date: 16.10.2017 09:02
Subject: RE: [SI-LIST] Re: Stacked microvia on high speed diff layer
transitions
Wolfgang, Ed,
I need to somewhat disagree. Ok, there is no *THEORETICAL* limit to the
number of microvias that can be stacked. But for sure there is an
economical limit.
This is a sequential process. And unfortunately, the intermediate steps /
sub-assemblies can not be fully tested. So a defect part may be processed
further.
Just for the sake of demonstration, let's assume that each sub-assembly
can be manufactured with a yield of 95%:
