[SI-LIST] Re: Stack up for EMI reduction,plane resonance and u-str ip radiation etc etc

From: "Craig Twardy" <ctwardy@xxxxxxxxxxxxxxxxxx>
To: istvan.novak@xxxxxxxxxxxxxxxx, weirsp@xxxxxxxxxx
Date: Fri, 13 Feb 2004 09:16:45 -0500
Steve, Istvan;
"the big V" can also cause ASICs to resonate at the die.
Usually the significant lossy component (dampening) is the ESR of "the big
V".
When this gets small, the ASIC package can become underdamped. 
"the big V" does not have to coincident exactly with the natural resonant
frequency of the ASIC Package.
It just needs to be somewhere close (within an octave or two can be
sufficient).

When this happens the noise seen at the PCB is usually low. 

I guess this goes back to a previous thread; without knowing the ASIC
package
And die components, power supply decoupling is a crap shoot.



Craig

-----Original Message-----
From: Istvan NOVAK [mailto:istvan.novak@xxxxxxxxxxxxxxxx] 
Sent: February 13, 2004 8:27 AM
To: weirsp@xxxxxxxxxx
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Stack up for EMI reduction,plane resonance and u-str
ip radiation etc etc


Steve,

Well said.  Given the fact that there is still hardly any bypass capacitor
on the market where the designer would have a known range for its ESR,
selecting the largest value cap in a ceramic case style, and creating a
single deep V seems to be a good working compromise.

There are two penalties associated with this solution.  At low frequencies,
where the V shape interfaces with the impedance of bigger capacitors, we
will have to pay a factor of two either in the inductance of the bigger caps
(need twice as many) or in the capacitance of the ceramic caps creating the
deep V (if we selected the biggest capacitance in the case style, this also
means we need twice as many).  There is a similar but more severe penalty at
high frequencies, where these ceramic capacitors interface with the planes,
let it be thin dielectric -:) or thick dielectric.  To sufficiently suppress
the capacitor-plane resonance and the first few plane modal resonances, the
cumulative inductance of the parts has to be several times less, which means
correspondingly more parts.  But I agree that given the circumstances this
is a safe working solution.

I hope sooner than later the industry will demand bypass capacitors with
specified ESR values (with +- tolerance) where the nominal ESR value can be
selected from a list, similar to nominal voltage, material, etc.

Regards,

Istvan



----- Original Message -----
From: "steve weir" <weirsp@xxxxxxxxxx>
To: "Bart Bouma" <bart.bouma@xxxxxxxxx>
Cc: <si-list@xxxxxxxxxxxxx>; <si-list-bounce@xxxxxxxxxxxxx>;
<zhang_kun@xxxxxxxxxx>
Sent: Friday, February 13, 2004 4:47 AM
Subject: [SI-LIST] Re: Stack up for EMI reduction,plane resonance and u-str
ip radiation etc etc


> Bart, I don't know why people fear that big "V".  Capacitors by the 
> decade are something that I oppose.  I have seen people, including 
> respected consultants mess up capacitors by the decade and blow 
> impedance targets by a factor of 3:1 or more.  In the meantime, no 
> parts were saved. There is nothing wrong with an impedance lower than 
> target, and the capacitor count is driven by the requisite inductance 
> to meet the HF intercept.  Take the same qty of capacitors using 
> decade spacing, and just substitute the larger value for all of them 
> and the impedance plot is
still
> very well behaved, and the phase doesn't go all over creation.
>
> The only argument that anyone could ever try and make for smaller 
> value capacitors that makes any sense to me is the higher ESR of the 
> small values, provided it is high enough to get close to Ztarget that 
> will help damp anti resonance with the planes.  In that case, I can 
> see clear to two values of ceramic caps properly chosen, but not by 
> the decade.  But, I
have
> yet to see any author who advocates multiple values of MLCCs advocate 
> on the basis of bringing up the ESR.  It has always been based on this 
> folklore surrounding some perceived need for a flat impedance curve, 
> that many then blow due to antiresonance.
>
> Regards,
>
>
> Steve.
>
>
>
>
> At 10:34 AM 2/13/2004 +0100, Bart Bouma wrote:
>
> > > Zhangkun, I am curious, why do you use capacitors as small as 1nF?  
> > > Do
you
> > > use capacitors spaced by decades, ie:  1uF 100nF, 10nF, 1nF?  If 
> > > so,
why
> > > not just use 100nF in an 0603 package?  They have the same 
> > > inductance
as
> > > any other value in that package, and with just one value they will 
> > > not
> > have
> > > an antiresonant peak.
> >
> >Steve,
> >you're right. There will be no parallel resonances in that case. But 
> >impedance will not be a 'flat' line over frequency. There will be one 
> >deep dip at the part's resonance frequency which typically will be 20
MHz.
> >
> >Using 1nF, 10nF etc. is not a bad idea: it results in a low impedance
over
> >a broad frequency range, with dips at regular intervals. This is a 
> >wellknown method that is used by many people I believe. By using 
> >low-Q parts, the resonance peaks can be controlled. The 1nF parts are 
> >most likely not the best wrt to low ESR values, so are
a
> >good choice I think.
> >More problematic are e.g. the 100nF 0603 parts, they have a large 
> >number of electrodes and hence a low ESR-figure. See attached plot: 
> >showing three curves for 1nF, 10nF and 100nF 0603
parts.
> >(sorry si-listers: attachment will be filtered out).
> >
> >best regards, Bart
> >Yageo Europe
> >
> >Re [SI-LIST] Re Stack up for .gif
> >
> >
> >
> >
> >steve weir <weirsp@xxxxxxxxxx>
> >
> >13-02-04 02:59
> >Sent by: si-list-bounce@xxxxxxxxxxxxx
> >
> >
> >Please respond to weirsp
> >
> >         To:        zhang_kun@xxxxxxxxxx
> >si-list@xxxxxxxxxxxxx
> >         cc:
> >         Subject:        [SI-LIST] Re: Stack up for EMI reduction,plane
> > resonance and u-str ip radiation etc etc
> >     Category:
> >
> >
> >
> >Zhangkun, I am curious, why do you use capacitors as small as 1nF?  
> >Do
you
> >use capacitors spaced by decades, ie:  1uF 100nF, 10nF, 1nF?  If so, 
> >why not just use 100nF in an 0603 package?  They have the same 
> >inductance as any other value in that package, and with just one 
> >value they will not
have
> >an antiresonant peak.
> >
> >Steve.
> >At 09:42 AM 2/13/2004 +0800, Zhangkun wrote:
> > >Dear all:
> > >
> > >I have reviewed the mails in this thread. The following is my 
> > >points.
> > >
> > >a)From my view, I am caring about the EMI of PCB. Very small common
mode
> > >noise will give rise to critical EMI problem. In my experience, the
common
> > >mode noise is proportional to the impedance of power delivery 
> > >systems. This has been verified by measurement and simualtion.
> > >
> > >b)I have done some measurement. No matter have many caps are placed 
> > >on
the
> > >boards, the impedance of PDS beyond 200MHz will not get better. It
should
> > >be clarified that now I do not use cap less than 1000pF. When the 
> > >caps less than 1000pF is used, there will be a lot of 
> > >antiresonance. This is also verified by simualtion and measurement.
> > >
> > >c)I have not studied the interaction between signal in trace and 
> > >noise
in
> > >plane. However, I have treated one case, in which the noise in 
> > >plane seriously affect the signal in trace. After we eliminate the 
> > >noise in plane, the signal become very good.
> > >
> > >Best Regards
> > >
> > >Zhangkun
> > >2004.2.13
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>
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>
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Follow-Ups:
- [SI-LIST] Best PDS impedance for package damping
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[SI-LIST] Re: Stack up for EMI reduction,plane resonance and u-str ip radiation etc etc

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