[SI-LIST] Re: Stack up for EMI reduction,plane resonance and u-str ip radiation etc etc

From: Chris Cheng <Chris.Cheng@xxxxxxxxxxxx>
To: si-list@xxxxxxxxxxxxx
Date: Tue, 17 Feb 2004 19:16:15 -0800
In my pursuit of getting an atta boy award for the 
longest thread in Si-list without yelling and shouting. 
I would like to keep the discussion going.

Recalling my claim that power distribution management
is really boils down to two common sense principles
(I will call this CSP from now on):

a) Manage core power distribution with a total system
approach. Highspeed on-die, medium speed on package
and low speed on PCB.
b) Manage your I/O signals with proper reference
plane and image current return.

The corollary of the above is fancy decoupling caps
and thin core PCB power planes are not needed because
the problem they try to solve can also be fixed by
following the above principles.

No doubt there has been many heated debates on CSP 
for the past few years in this Si-list. And either
you buy it or you don't. There is really no point 
for me to continue the debate.

However, there is a persistent point in the argument
of needing thin core/fancy capacitors that I have 
not seen a definitive answer on and I really would
like to drill deeper into the discussion.

This is the area of "containment" vs. "suppression/
decoupling" when system functionality is not in 
trouble while failing EMI noise limit is the concern.


Here is some quote from members of the list :
Ray :
>The low-pass characteristics of the package are not 
>"brick-wall" in nature but have a finite amount of 
>attenuation. You can't really say that the package 
>attenuates all the noise emanating inside to 
>insignificant levels. The noise is attenuated, 
>but some is still there and can excite resonant 
>structures.

Steve :
>There is one point that I disagree on.  Even though 
>the package cuts off with at least a -2 slope, 
>there is quite of bit of high frequency energy 
>that still passes between the PWB and the IC.  
>It is just grossly inadequate to power the IC.  
>But it has lots of potential to aggravate EMI 
>problems.

Zhangkun :
>From my view, I am caring about the EMI of PCB. Very 
>small common mode noise will give rise to critical 
>EMI problem. In my experience, the common mode noise 
>is proportional to the impedance of power delivery 
>systems. This has been verified by measurement 
>and simulation.

I have to admit I am a system designer, not component
engineer like Larry and Ray or EMI engineer like 
Zhangkun and Istvan. Even though I have worn these
hats when needed, at the end of the day, I only
try to answer the question : "can my bus/chip/system
function given the power distribution system I 
design ?" And CSP is really guiding me to make sure
my core power noise is within limits and at the 
same time does not generate enough noise back to 
the system to cause other components to fail
noise margin. On the I/O side, CSP guides me to
prevent image current mis-management to cause both
EMI radiation and SSO noise. 

But the above principles say nothing about residue
noise that is small enough not to create functional
problem on the system but large enough to 
potentially create EMI noise. And I believe 
that's what Ray, Steve and Zhangkun is arguing 
above. I still don't think there is an argument 
that you need fancy caps or thin core just to 
make your system functional if you follow CSP.

So the question is, how does one quantifies when 
is it time to "suppress/decouple" EMI noise on
the system (be that using fancy caps/thin core or
just conventional capacitor solutions) and
when does one just need containment (by bury
noisy power planes inside, ground stitching vias
on PCB, metal casing, copper gaskets etc etc).

We are talking about over-designing decoupling 
solutions here, ie like Ray or Steve say, may
be you have an on die noise of +/-100mV@400MHz
on a 1.5V design, after the noise propagate 
through the package, it creates a +/-20mV 
of ripple on the PCB. Clearly not big enough
to cause functional failure but "The noise 
is attenuated, but some is still there and 
can excite resonant structures." or "It is 
just grossly inadequate to power the IC.  
But it has lots of potential to aggravate 
EMI problems." 

How low do we need to go ?
How can one predict these noise will create
EMI problem ?

As a server or computer designer, I have the
luxury of always having metallic chasis/
gaskets, reasonable cables and connectors.
So I always fall back to ignoring the above
below functional acceptable level noise and
allow my containment solutions to deal with
it. The only thing I will do extra is
buring potentially noisy power planes inside
and stitching ground vias in PCB. And, knock
on wood, so far any thing I am responsible 
seems to be passing EMI just fine if I 
follow CSP.

But I welcome anyone to explain to me how
you can quantify the need to suppress these
below functional noises in a predictable 
manner. i.e. I am not looking for an 
answer like "hey, when you fail EMI, 
you should look into doing X,Y,Z." Rather 
I am looking for an answer like "if you 
do X,Y,Z, my analysis tells me you can 
throw away your gasket or your metallic 
chassis." What will be really interesting 
is something like "if you follow CSP but 
you don't have fancy caps or thin core 
planes, my analysis predict your system 
will fail EMI." You will for sure have 
my attention then. 

Any takers ?
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[SI-LIST] Re: Stack up for EMI reduction,plane resonance and u-str ip radiation etc etc

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