[SI-LIST] Re: Splitting this power plane - And GND planes count

  • From: Ivor Bowden <ivor@xxxxxxxxxxx>
  • To: Sol Tatlow <Sol.Tatlow@xxxxxxxxxxxxxxx>
  • Date: Mon, 14 Mar 2005 10:39:22 -0800

Thank you for your detailed comments! I will not be flooding the
internal signal layers in the asymmetrical stripline area for impedance
control reasons. We do have a variety of products, the target audience
varies along with cost concerns. I have to make do the best I can with
the constraints I have. Hopefully we will find a compromise with this
board that will perform adequately..

on 3/12/2005 3:57 PM Sol Tatlow wrote:

>While I agree with Alan that his stackup, at cost of 'only' 2 more layers, is 
>a huge improvement, it seems to me, that noone answered your original 
>question: "it
>shouldn't hurt to split layer 9?". Plus, Alan's idea doesn't really help you 
>with regards to the
>additional power planes you have spread across 3 _signal_ layers .... In fact, 
>if you took
>his advice, and STILL split the same power plane, it could look even worse for 
>the signals
>on the neighbouring signal layer. Plus Gil's question (GND floods) remains 
>unanswered ...
>1. Relating to your original plan: while layer 7 may be well bypassed, are you 
>sure the
>Signals on layer 8 are referencing to that layer? Depends upon source voltages 
>and core/
>prepreg thickness, I would have thought ... At any rate, with a significant 
>split in the plane,
>you will in any case get a trace impedance mismatch, if only small, at the 
>split. AND, any
>components on the bottom side in this area, without their own tightly coupled 
>GND planes
>will very likely be, as Steve said, an EMC problem.
>2a. You flood all signal layers with GND 'to make up for only 1 GND plane' ... 
>Sounds like
>a good idea in theory, BUT, from my experience, a board that is dense enough 
>need 4 inner signal layers has no space on those layers in those areas where 
>the extra
>GND flood would be of real benefit ... AND it certainly won't help the 
>components on the
>bottom side in that split plane area. MIGHT help with overall current capacity 
>2b. PLUS, the ground flood will, of course, affect the impedance of any tracks 
>adjacent to the
>GND floods. Not so bad for layers 3 and 8, where there are no neighbouring 
>signal layers, but
>for 5 and 6, if you have controlled/targeted impedance lines (and LVDS usually 
>are), you are
>asking for multiple swings/steps in trace impedance as signal traces 
>enter/leave GND floods
>on neighbouring layers, which is going to be bad news. Same goes for power 
>islands on
>signal layers with neighbouring signal traces, of course.
>3. Gil: IF you GND flood the signal layers, you should look to get a good 
>between lots of GND vias and carving up the power planes. If you are limited 
>to very few GND
>vias, look to place them well - for example, in the vicinity of large busses 
>changing layers:
>with busses referenced to multiple GND layers (if you have them!) this will 
>improve return
>current paths.
>Anyway, having looked at your website, Ivor, I see you work in 
>military/medicine areas, where
>I would have expected the extra dollars for the 10 up to 12 layer step to be 
>an investment. At
>least get it quoted - it may be less than you think. For example, on my latest 
>project (17,500
>pin board) I went for 26 instead of 18 since the price increase was only 
>marginally over 10%!!
>This increase in layer count allows me to double up 2 of the 4 power layers 
>(and yes, I NEED
>4 different power layers thanks to large pin count Xilinx FPGAs with up to 4-6 
>different supply
>voltages in the same area!), as well as adding more 'GND/PWR cavities'.
>And then, if you go from 10 to 12, take Alan's stackup, since, as Steve said, 
>this will majorly
>help on the EMC side of things (with extra GNDs), and add pairs of PWR/GND 
>floods on sig
>layer pairs where needed, PLUS judiciously chosen split planes to give you the 
>3 power
>layers you need without disrupting signal impedances. With the right 
>combination, you will
>get more than ample current capacity, multiple GND/PWR pairs, and an excellent 
>without too much of a compromise with regards to signal trace impedance or 
>Good luck!
>Sol Tatlow, M.Eng. (Oxon)
>ProDesign Electronic & CAD Layout GmbH
>Product Developer
>Albert-Mayer-Str. 16
>D-83052 Bruckmuehl
>Phone: +49 (0) 8062-808-302
>Fax:   +49 (0) 8062-808-333
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