[SI-LIST] Re: Split planes and ground return wires
- From: "Godbout, Marc" <marc.godbout@xxxxxxxxxxxxxx>
- To: "'howiej@xxxxxxxxxx'" <howiej@xxxxxxxxxx>, si-list@xxxxxxxxxxxxx
- Date: Thu, 20 Feb 2003 14:00:47 -0500
Thanks, Dr. J. It's great to get feedback from the guy that "wrote the
book" (literally). This is one of those cases where I need ammunition to
back up what I felt in my gut from experience.
The .2" is correct, although totally out of our control. We're using fairly
thin PCB's and metallic core to meet our board space requirements. The
component max height alone is extremely restrictive.
But considering mutual inductance, wouldn't the parallel traces leading to
the z-axis wires be even more of a controlling factor? And how does the
metallic core effect these wires? The core is tied to chassis ground, and
each wire has its own hole.
Also, standard CMOS edge rates apply.
-Marc
> -----Original Message-----
> From: Dr. Howard Johnson [SMTP:howiej@xxxxxxxxxx]
> Sent: Thursday, February 20, 2003 12:37 PM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: Split planes and ground return wires
>
>
> Dear Marc,
>
> You have raised what is (to me) a very interesting question,
> one which deserves a good analytical answer.
>
> If we just deal with a group of ten signals surrounding one
> nearby ground return wire, there are some analytical tools
> that can help you predict the answer.
>
> First, you need to know the mutual inductance between
> signals
> in your configuration.
>
> Given an aggressive wire at position a, and a victim wire at
> position v, and one and only one ground wire at position g,
> all traversing z-axis distance h, if I recall correctly the
> formula for the mutual inductance shared between the
> aggressor
> and victim is:
>
> Lm = 5.08 * h * [ln(|v-g|/R) - ln(|v-a|/|g-a|)]
>
> where R is the radius of the wire,
> the dimensions h, |v-g|, |v-a|, |g-a|, and R are inches,
> the function ln() is the natural logarithm, and
> the answer Lm appears in nH
>
> As you can see the wire radius R appears as a logarithmic
> term in the equaltion and so changes in the wire radius do
> not strongly affect the outcome. The height h of the cavity
> between the boards (the wire length) affects the result
> directly and is thus your most powerful control variable.
>
> Let's do an example with the positions a, v, and g in a
> straight row with equal spacing s=0.1 inch.
>
> |v-a| = .1
> |v-g| = .1
> |g-a| = .2
> R = .01 (radius of 24 AWG wire)
> h = .2 (from your note, although this sounds awfully
> tight)
>
> Lm = 5.08 * .2 * [ln(.1/.01) - ln(.1/.2)]
>
> Lm = 3.04 nH
>
> You should re-run this example assuming the only return
> paths
> are provided by the so-called "low inductance" ground pins
> in your backplane connector. Because they are located
> further
> away from the signals, the mutual inductance Lm will come
> out
> larger -- thus the importance of locating the return paths
> near the signals.
>
> The next issue has to do with your signal risetimes. The
> risetime (not the operating speed) determines the bandwidth
> of
> your signals. Assuming you are working with a modest CMOS
> process having rise/fall times on the order of Tr = 1 nS,
> the
> bandwidth (upper-bounded by approximately 0.5/Tr) works out
> to f = 500 MHz, at which frequency the impedance Zm
> represented
> by the mutual inductor Lm at frequency f
> equals Zm = 2*pi*f*Lm = 9.55 ohms.
>
> The crosstalk you receive has to do with the ratio of Zm to
> the
> circuit impedance Z0. If you were using end-terminated
> transmission
> lines with Z0=50 ohms, the numbers in this case indicate a
> crosstalk of approximately 9.55/50 = 19 % FOR EACH
> AGGRESSOR.
> Fortunately, in your application the wires are quite short
> compared
> to 1 ns and so they are likely not terminated, in which case
> the
> current drawn on each wire (and thus the mutual-inductive
> crosstalk)
> will be considerably less than 19 %.
>
> By the way, if you are using source-terminated lines the
> current
> waveform produced on the wire appears as two steps, one
> positive
> followed by one negative, with amplitudes equal to
> (1/2)Vcc/Z0
> and separation in time approximately equal to the line delay
> (depending on where along this line your "connector"
> appears).
> If the line length, and thus the separation of the two
> opposing
> current waveforms, is small compared to the risetime the
> two opposing chunks of mutual-inductive crosstalk created in
> this configuration tend to cancel out.
>
> Lastly, the crosstalk that concerns you in this example
> bears a
> striking resemblance to the crosstalk that occurs when
> ordinary
> vias traverse a pcb. In analyzing those situations one takes
> into
> account all the nearby return paths, which tends to diminish
> the
> value of Lm quoted above for a single return path. Software
> for
> such calculations is provided by, among other companies,
> Sigrity.
>
> Best regards,
> Dr. Howard Johnson, Signal Consulting Inc.,
> tel +1 509-997-0505, howiej@xxxxxxxxxx
> http:\\sigcon.com -- High-Speed Digital Design articles,
> books, tools, and seminars
>
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Godbout,
> Marc
> Sent: Wednesday, February 19, 2003 6:57 AM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Split planes and ground return wires
>
>
>
> I've got questions concerning ground return wire
> requirements and hope the
> list can help. First the configuration.
>
> Our system as got boards that are physically two separate
> PCB's, about 6" X
> 7", sandwiching, and bonded to, a metal plate. Signals need
> to traverse from
> one PCB to another. To accomplish this, we run wires through
> holes in the
> plate. These signals are basically microprocessor-type
> signals, 5V CMOS. The
> bus speeds are 25MHz or lower.
>
> Ground returns are added at about a 10:1 ratio, and placed
> somewhat near the
> groups of signals. The ground planes are also connected to
> each other
> through the backplane connector through 40 low-inductance
> pins.
>
> So I see this as a not-quite classical split plane problem.
> The split is
> crossed by 40 connector wires and maybe 15 z-axis wires,
> each 0.200" long.
>
> We've got some mechanical constraints that are making me
> look into the
> minimum requirements of the ground return wires. I feel that
> the "bigger is
> better" theory was used to design them in the first place,
> but I've got to
> cut back on that right now. So the question is, by how much?
>
> So what are the areas or major concerns that I should
> investigate? How do I
> go about calculating a minimum wire size? And are there any
> texts that would
> help me zero in on my analysis methods?
>
> Thanks for any help you could give.
>
> -Marc
>
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