[SI-LIST] Re: Spice to IBIS
- From: "Muranyi, Arpad" <Arpad_Muranyi@xxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Mon, 20 Jul 2009 08:30:27 -0700
By the way, you may want to read the IBIS Cookbook.
http://www.vhdl.org/pub/ibis/cookbook/cookbook-v4.pdf
There is a lot of good information (including this
topic) in that document...
Arpad
======================================================
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Muranyi, Arpad
Sent: Monday, July 20, 2009 10:25 AM
To: In-myoung Song; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Spice to IBIS
You are not required to use .DC to generate I-V curves
for IBIS. In fact you are better off if you stay away
from using .DC for the reason you bring up. Large
buffers with lots of flip flops inside need a few clock
cycles before the output gets into a known state.
You can generate I-V curves using the .TRAN mode. All
you need to do is a PWL voltage source connected to
the output of the buffer. Force the voltage, measure
the current, you got an I-V curve. Just make sure that
your waveform in the PWL source is not ramping too fast,
otherwise you will introduce an error current which
comes from the parasitic capacitance in the buffer:
I=C*dV/dt. When the slope of the PWL source is slow
enough, this error current becomes negligible.
Arpad
========================================================
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of In-myoung Song
Sent: Monday, July 20, 2009 3:03 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Spice to IBIS
Hello!
Many disscussion were over about Spice to IBIS conversion.
But I can't find the exact answer about below problem.
If the Spice Model of one I/O buffer model has a clock pin, and the
output is synchronouse by that clock,
in the spice simulation for I/V curve we need to add the clock stimulus
and .Tran analysis, right?
But simulation for I/V curve, we should sweep the voltage at I/O pad
from -Vcc to 2Vcc.
This is .DC analysis right?
In spice simulation can we simultaneously simulate .DC and .Tran ?
That is confusing....
Thanks alot!
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