[SI-LIST] Skin effect resistance in package pins for IR drop calculations
- From: Mohan R <mohanr_india@xxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Wed, 24 Aug 2005 15:45:58 +0100 (BST)
Dear Experts,
I had a question on the the pin(bondwire+leadframe)
resistance to used for IR drop calculations for the
digital core logic. Do i need to consider the
resistance at DC or do i need to consider the
resistance with skin effect included ?
I was guessing that the high frequency current for
digital core CMOS transistors will be supplied by
decoupling capacitors on the chip. Hence only the DC
current for charging the decoupling capacitors would
be provided by the package pins.
Please comment.
Thank you,
Mohan R
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