[SI-LIST] Re: Skin effect resistance in package pins for IR drop calculations
- From: steve weir <weirsi@xxxxxxxxxx>
- To: mohanr_india@xxxxxxxxx, si-list@xxxxxxxxxxxxx
- Date: Wed, 24 Aug 2005 08:18:40 -0700
Mohan, if you are not planning to model skin resistance, does that mean
that you also do not plan to model loop inductance? How slow is your circuit?
Steve.
At 03:45 PM 8/24/2005 +0100, Mohan R wrote:
>Dear Experts,
>
>I had a question on the the pin(bondwire+leadframe)
>resistance to used for IR drop calculations for the
>digital core logic. Do i need to consider the
>resistance at DC or do i need to consider the
>resistance with skin effect included ?
>
>I was guessing that the high frequency current for
>digital core CMOS transistors will be supplied by
>decoupling capacitors on the chip. Hence only the DC
>current for charging the decoupling capacitors would
>be provided by the package pins.
>
>Please comment.
>
>Thank you,
>Mohan R
>
>
>
>
>
>
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