[SI-LIST] Re: SSTL-2 series termination in DDR Applications
- From: Vinu Arumugham <vinu@xxxxxxxxx>
- To: dcs@xxxxxxxxxxxxxxxx
- Date: Thu, 06 Jun 2002 13:08:43 -0700
"D. C. Sessions" wrote:
> On Thu, 2002-06-06 at 00:30, Anand.Kuriakose@xxxxxxxxxx wrote:
>
> > Why is it required to provide series termination on the DDR signals (SSTL
> > logic)
> > on the motherboard when the DDR DIMMs themselves have series termination on
> > every signal (as the SSTL spec states) ? I think we can get reliable signal
> > quality without these series terminaters on the motherboard. Correct me if
> > i am
> > wrong.
>
> The memory array section on the motherboard has so much dense
> loading on it that the effective impedance there is closer to
> 25 than 50 ohms (thus the ~27 ohm shunt terminators).
>
> On the other hand, as hard as the board manufacturers try, it's
> almost impossible to reduce the lead-in line from the controller
> to the memory below 50 ohms. The result is a mismatch at the
> first memory device.
In one application, we found that using two 50 ohm lines routed in parallel
between
memory and controller to provide an equivalent 25 ohm interconnect was easier to
implement than introducing series resistors.
Thanks,
Vinu
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