[SI-LIST] Re: SSO doubt
- From: Jory McKinley <jory_mckinley@xxxxxxxxx>
- To: starsilic@xxxxxxxxx, si-list@xxxxxxxxxxxxx
- Date: Wed, 4 Apr 2007 11:25:43 -0700 (PDT)
Hello Canes,
While SSO is an issue for quite I/O's (for example a sampling of a quite net in
the face of enough noise to create a false state). The main issue that we have
run into has to due with timing pushout/pullin on the active nets which are
effected by the noise on the power rails due to multi-switching nets as well as
the crosstalk noise in the package and on the board created by these same nets.
In your simulations take a look at the timing at the receivers of the switching
nets while exercising the various driving patterns.
-Jory
Canes Venatici <starsilic@xxxxxxxxx> wrote: Hi all,
I did SSO simulation using I/O cell spice model, package models, Transmission
line model and i/p model of the receiver.
I could see the quite node is getting noise because of the neighborhood I/O
pads are switching simultaneously. The quite node noise is crossing the
Vil(max), assuming the pad is driven with DC 0v (gnd). But the noise is like
pulses with triangular like shapes. I'm having difficulty in deciding whether
this can cause the problem in the receiver. I mean, at what pulse duration, at
a particular voltage above Vil, can cause false i/p to the receiver.
Like Vil(max), are there any parameters which describes the minimum energy
required to consider as an i/p by the receiver?
Regards
Canes.
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