hi, I could see the SSO results strongly depends on the package parasitics, esp. Inductance. We are in the process of selecting the package, die size etc. Even though we fixed the number of pins for the package, we are still in the process of finding the split-up of power and signal pins. But for deciding number of power /signal pins, we need to do SSO simulation, which again depends on package parasitics. For example, if I go with say around 2nH as the package inductance I could get the pin count as spec. But if I go to say 10nH, its exceeding the spec heavily. How to solve this chicken-egg problem? Please correct me if I'm wrong in the system approach. Regards Canes __________________________________________________ Do You Yahoo!? Tired of spam? Yahoo! Mail has the best spam protection around http://mail.yahoo.com ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List technical documents are available at: http://www.si-list.net List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu