[SI-LIST] Re: SSO SSTL Vs LVTTL
- From: Canes Venatici <starsilic@xxxxxxxxx>
- To: "Peterson, James F \(EHCOE\)" <james.f.peterson@xxxxxxxxxxxxx>
- Date: Thu, 3 May 2007 02:49:26 -0700 (PDT)
Jim,
Thanks for your answer. I want to explain in-depth, why I considered cap. of
T.line.
FYI, I'd not lumped the transmission line i/p capacitance as a load cap. First,
I'd put transmission line
at the o/p of the driver and seen the rise time at the i/p of T.line(Tr), just
before the reflection causing the
near end signal getting distorted.
Then I'd swept the lumped load cap (replaced T.Line load) at the o/p of driver
and seen where the rise
time matches. I could find some value. It matched exactly with the calculated
capacitance of T.Line
(C=Td/Zo). Then I assumed L can also be calculated similarly, (L=Td*Zo).
------------------------ Calculations---------------
I assumed 4in lossless transmission line, Prop. velocity = 1.5e8 m/s, Zo=50.
So 666.6ps is the delay and C= 13pF, L=33.3nH
--------------------------------------------------------
Our first problem was whether we need lumped model or distributed model for the
load. For that I calculated the
electrical length (length of rising edge), by Tr/[delay(ps/in)]. I'd seen the
rise time and length of transmission
lines makes me to use distributed model (trace length >= electrical length/2).
This made me to ask the question below,
I could see in some documents, the SSO simulation set up for SSTL2 interface is
like below.
I want to know whether the schematic below represents the correct simulation
set-up for SSTL2 quite node
SSO simulation including T.line effects.
I tried inserting transmission line between Rser and Cload-Rt junction. But I
get very different values
of noise compared to the results provided in the doc, which is using the below
set-up.
Could anyone explain which is correct method and how the schematic below can
represent the
T.Line effects.
Actually in the simulation I'd added the package modeling for power
distribution also, but not shown here.
VTT
____
|
|
/
\
Rt
/
\
------------ ---------- |
| | | | Rser
|
| Driver |-------| Pkg | ------------/\/\/\/\/\/\----------|
| | |
model
| |
| | | |
|
------------
------------ |
====
Cload
|
|
|
_____
__
-
Regards
Canes
----- Original Message ----
From: "Peterson, James F (EHCOE)" <james.f.peterson@xxxxxxxxxxxxx>
To: Canes Venatici <starsilic@xxxxxxxxx>
Sent: Wednesday, May 2, 2007 5:34:19 PM
Subject: RE: [SI-LIST] SSO SSTL Vs LVTTL
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Canes,
That?s the beautiful and remarkable
thing about transmission lines. They do not distort, only delay. The
reason they don?t distort is because the t-line looks resistive, not
capacitive or inductive. And, indeed, this is what the edge of your
signal sees (not the steady state portion of your signal).
For a couple references see page 143, last
paragraph, of Dr. Johnson?s book ?High Speed Digital Design ?Black
Magic? and the last 2 paragraphs of page 295 of Ron Poon?s ?Computer
Circuits Electrical Design?.
If you have a 10 inch t-line at 4pf per
inch, you can?t add up the C per inch and replace it with a 40pf cap
because ?the capacitive effect is tuned out by the inductive effect, and
the ladder network just acts as an ideal delay line : it does not degrade the
signal risetime and falltime? (R. Poon).
Jim Peterson
From: Canes Venatici
[mailto:starsilic@xxxxxxxxx]
Sent: Wednesday, May 02, 2007 3:03
AM
To: Peterson,
James F (EHCOE)
Subject: Re: [SI-LIST] SSO SSTL Vs
LVTTL
Jim,
Could you tell me why, for the drivers the T-lines are seen as resistive load?
Why I'm asking is during transients only SSN occurs. During that time, the
drivers see the T.Lines as inductors and capacitors/unit length, is my
understanding.
Probably during steady state they (T.Lines) can be seen as resistive loads.
Could you correct/explain me if I'm wrong?
Regards
Canes.
----- Original Message
----
From: " Peterson, James F
(EHCOE)" <james.f.peterson@xxxxxxxxxxxxx>
To: starsilic@xxxxxxxxx
Sent: Tuesday, May 1, 2007 1:05:55 AM
Subject: RE: [SI-LIST] SSO SSTL Vs LVTTL
From what I have seen, and it?s
mostly been the results from simulators and what I?ve read, so I
don?t have a lot of lab data to back this up, using this approach of
approximating the SSO current with the source impedance is pretty
accurate?that said, you do have to figure out what the source-Z is, but
there are a couple excellent ways to do that.
Your second paragraph below is not
clear to me. I?m not sure I understand the question, but remember that to
a driver, t-lines look resistive, not capacitive or inductive. You can?t
lump together the C and L.
-Jim
From: Canes Venatici
[mailto:starsilic@xxxxxxxxx]
Sent: Monday, April 30, 2007 9:13
AM
To: Peterson,
James F (EHCOE)
Cc: si-list@xxxxxxxxxxxxx
Subject: Re: [SI-LIST] SSO SSTL Vs
LVTTL
Jim Peterson,
Thanks for your reply. The only concern is the impedance of the driver may be
non-linear,
depending upon the state (cut-off/linear/saturation) of the transistors, so I
was wondering
can we approximate the driver impedance.
Also I've one more doubt regarding the simulations using T.Lines. I used 4inch
lossless transmission line.
The equivalent i/p inductance comes around 33nH and capacitance comes to be
13pF, by simple formulas
of T.lines. With this if I do simulations, I get very high power cell
requirement for each signal cell, or the quite node
noise is very high.
I could see in some docs related to SSO simulations, they were just putting
series resistor at the output of the driver, followed by
termination resistor pulled to Vtt for SSTL interfaces, instead of T.lines in
their SSO set-ups.
Could anyone clarify on how well it can represent SSO noise simulations?
Regards
Canes
----- Original Message
----
From: " Peterson, James F
(EHCOE)" <james.f.peterson@xxxxxxxxxxxxx>
To: si-list@xxxxxxxxxxxxx
Cc: starsilic@xxxxxxxxx
Sent: Monday, April 30, 2007 5:07:14 PM
Subject: RE: [SI-LIST] SSO SSTL Vs LVTTL
Hello Canes -
Since you're measuring noise at a quiet node, I assume you are
discussing SSO noise. I'm going to step out a little here and make a
bold statement : if you are comparing the SSO characteristics of two
different technologies, say 2.5V LVTTL and 2.5V SSTL, and their rise
times are the same, and their source impedances are the same, then their
SSO noise will also be the same. So, based on that statement, changes in
these above mentioned items will cause the SSO to change. If you go to a
stronger driver or a larger voltage swing (3.3V LVTTL) - and the rise
time stays the same - then you've increased SSO noise. If you go with a
weaker driver, or you put a series resistor at the output (like SSTL)
then the SSO noise will decrease. Signal swing, rise/fall time, and
source-Z are the things that influence SSO noise.
As a side note, you mention "12ma driver". IC manufacturers use this
as
a DC drive number not an AC number. That's why we should use the source
impedance of the driver as a better (but not perfect) description of a
driver's capability.
Regards,
Jim Peterson
Honeywell
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Canes Venatici
Sent: Monday, April 30, 2007 1:18 AM
To: si-list@xxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] SSO SSTL Vs LVTTL
Hi,
I did quite node simulations in LVTTL and SSTL class I and II pads. I
used transmission line models for all the
simulations with noise measured at the Far End.
I tried to operate the LVTTL pads at 3.3V with 12mA drive strength. I
could see
the noise is more than with SSTL2-I/II interface.
Since there were no terminations for LVTTL, I suspect it can give more
noise compared to
SSTL. Comments are appreciated.
Even between SSTL2-I and II the power:signal is nearly same (the quite
node noise is similar),
with class-II is slightly more than class-I and in lower power:signal
ratios, the noise is less in
class-II compared to class-I.
I feel SSTL2-class-II have two terminations, which makes the interface
less noisier compared
to SSTL2-Class-I. Comments are appreciated.
Regards
Canes
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