[SI-LIST] Re: TFT display modules with _min_ dot clock frequency spec

  • From: Dimiter Popoff <dp@xxxxxxxxxxx>
  • To: <si-list@xxxxxxxxxxxxx>
  • Date: Thu, 3 May 2007 1:20:17 +0300

> Min clock rate for dynamic logic would be expected in the tens of
> kilohertz, hundreds of kilohertz at most.  Similarly, the time constant
> on a TFT LCD cell is in hundreds of milliseconds, or even seconds (per
> your experiment), so that should not be a constraint.  

Sure, these have been my thoughts as well all along; the thing with
my experiment is it was done about 5 years ago when they did not
specify min. clock frequency.

> However, the dot
> clock range you mentioned in a previous answer is suspiciously narrow,

It is indeed, seems too narrow for a PLL as well for that :-). 

My guess is that it is contrained from below by the necessity to guarantee
the optical contrast and from above by sheer circuitry speed, hence
the narrow range. Not too appealing to low power products, doubling the
memory -> display frequency is significant both as overhead and
as power consumption.

In my current design, without sacrificing a great simplification
(think removing a 256 ball BGA chip) I can go to 16 MHz 16 bits per pixel
clock easily and I can - sacrificing some functionality which I probably
won't need anyway - go up to 24 MHz (obviously adding the memory
power and overhead, which I can afford but :-).

The display I have in mind looks really nice - have a look at it,

http://www.gifar.com.tw/pdf/TFT/GFT080BB800600-DL(SPEC).pdf .

They promised to come up with some answers when they would reach the
engineers, hopefully I will be able to use it after all.

Dimiter

------------------------------------------------------
Dimiter Popoff               Transgalactic Instruments

http://www.tgi-sci.com
------------------------------------------------------


> To: dp@xxxxxxxxxxx
> Date: Wed, 2 May 2007 14:05:52 -0700
> Subject: Re: [SI-LIST] Re: TFT display modules with _min_ dot clock frequency 
> spec
> From: olaney@xxxxxxxx
>
> Min clock rate for dynamic logic would be expected in the tens of
> kilohertz, hundreds of kilohertz at most.  Similarly, the time constant
> on a TFT LCD cell is in hundreds of milliseconds, or even seconds (per
> your experiment), so that should not be a constraint.  However, the dot
> clock range you mentioned in a previous answer is suspiciously narrow,
> and smells like a PLL is involved.  My LCD experience is from designing
> TFT panel driver circuitry, rather than using that of others, so I'm used
> to being less constrained.  It might be that you can take your time
> placing pixels in a FIFO buffer, then send the data in bursts one line at
> a time.  Likewise, you could have a 25 MHz or so oscillator for the panel
> & FIFO, but divide it down for use by the rest of the application.  I
> presume that the panel has the usual status signals so that you can
> demarcate valid data.  In other words, it might be possible to send the
> total frame at slower rates, so long as you honor the pixel clock rate in
> doing so.
> 
> Regards,
>                Orin
> 
> On Wed, 2 May 2007 23:25:05 +0300 Dimiter Popoff <dp@xxxxxxxxxxx> writes:
> > > Dimiter unless there is some really crummy dynamic logic, ...
> > 
> > Well the entire TFT matrix is dynamic, after all. And 60 Hz refresh
> > frequency is not that high, 16.7 mS... so may be twice that will be
> > visible, or perhaps just measurable (some do specify 400 times 
> > contrast
> > ratio, which is a lot). But if I knew I'd get half the contrast,
> > that is, 200, I'd be fine, my main problem is not to design a board
> > that will not be able to work with its display at all...
> > 
> > > I suspect that is actually a maximum clock rate / minimum clock 
> > > interval and is a victim of Japanese to English translation.
> > 
> > That's what I thought when I encountered such a spec first.
> > But then I saw it over and over again, at different manufacturers,
> > and it definitely does not look like a translation error.
> > My latest guess/hope is that they specify that in order to 
> > guarantee
> > the optical contrast spec, which might degrade at lower frequencies
> > and may be over temp. (OK, over the narrow temp range TFTs work
> > I doubt the gate capacitors of the matrix will change behaviour
> > a lot but then I may be surprised on that as well).
> > 
> > Dimiter
> > 
> > ------------------------------------------------------
> > Dimiter Popoff               Transgalactic Instruments
> > 
> > http://www.tgi-sci.com
> > ------------------------------------------------------
> > 
> > 
> > > 
> > > Date: Tue, 01 May 2007 22:35:49 -0700
> > > To: dp@xxxxxxxxxxx
> > > From: steve weir <weirsi@xxxxxxxxxx>
> > > Subject: Re: [SI-LIST] TFT display modules with _min_ dot clock 
> > frequency spec
> > > 
> > > Dimiter unless there is some really crummy dynamic logic, or as 
> > you 
> > > mention a PLL involved it doesn't seem to make sense to me either. 
> >  I 
> > > suspect that is actually a maximum clock rate / minimum clock 
> > > interval and is a victim of Japanese to English translation.
> > > 
> > > Steve.
> > > At 06:21 PM 5/1/2007, you wrote:
> > > >Posted this to two newsgroups, then I thought actually I might 
> > have
> > > >better chances to find someone in the TFT module industry via 
> > the
> > > >Si-list, so here it goes.
> > > >
> > > >I have been looking around for a TFT module for a design (5" to 
> > 8"
> > > >sized, 800x480 min.,thin) and found some really good looking.
> > > >  The problem I have is that some of them specify a minimum dot 
> > clock
> > > >frequency, typically well above 25 MHz.
> > > >  Now apart from a PLL they may have inside the module I can 
> > think
> > > >of little reasons why they need that; and I have not heard of 
> > such a
> > > >thing, but I am far from the insides of these (hence my posting 
> > :-).
> > > >  I could pretty well live at a 30 Hz or even 20 Hz frame rate,
> > > >which would mean 16 MHz clock or below, thus lower power,
> > > >less memory bandwidth etc.
> > > >  TFTs don't flicker, I have played with the first one I had 5-6 
> > years
> > > >back and there was absolutely no visible benefit of increased 
> > clock
> > > >frequency.
> > > >
> > > >Anyone know why this minimum clock spec? Any knowledge on that?
> > > >Some of the best fits I find do specify it and it is in conflict 
> > with
> > > >a really major simplification I can make to the design....
> > > >So my hope is that this spec is put in order to keep some high 
> > enough
> > > >frame rate to satisfy some common controller thing, not really a 
> > must.
> > > >I'll try to ask the manufacturers directly, but perhaps I have a
> > > >better chance to find out something via usenet.
> > > >
> > > >Thanks,
> > > >
> > > >Dimiter
> > > >
> > > >------------------------------------------------------
> > > >Dimiter Popoff               Transgalactic Instruments
> > > >
> > > >http://www.tgi-sci.com
> > > >------------------------------------------------------
> > > >


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