[SI-LIST] Re: SDRAM connection
- From: Adeel Malik <AdeelM@xxxxxxxxxxx>
- To: Alex Burman <AlexB@xxxxxxxxxx>
- Date: Wed, 17 Sep 2003 15:10:34 +0500
Hi Alex,
In fact I just wanted to know that what are the points that need to
be kept in consideraton while connecting a standard JEDEC standard SDRAM to
a little-endian processor or big-endian processor. I mean how should I swap
the row,column and bank select lines of the SDRAM with respect to the
little-endian/big-endian processor signals.
Regards,
ADEEL MALIK,
-----Original Message-----
From: Alex Burman [mailto:AlexB@xxxxxxxxxx]
Sent: Sunday, September 14, 2003 11:58 AM
To: AdeelM@xxxxxxxxxxx
Subject: RE: [SI-LIST] SDRAM connection
What kind of processor are you using?
Alex Burman
Hardware Engineer
Radlan
Computer Communications Ltd.
Atidim Technological Park, Bldg 4.
Tel Aviv 61131, Israel
Tel: 972-3-765-79-65
Fax: 972-3-645-85-39
alexb@xxxxxxxxxx
www.radlan.com
-----Original Message-----
From: Adeel Malik [mailto:AdeelM@xxxxxxxxxxx]
Sent: Thu, September 11, 2003 6:05 PM
To: 'si-list@xxxxxxxxxxxxx'
Subject: [SI-LIST] SDRAM connection
Hi All,
I need to connect 32M8 256Mb SDRAM to a processor. The SDRAM has
13 Address Lines for Row Decoding (8K rows) and 10 Address lines for column
decoding (1K columns) and two additional address lines BA0 and BA1. I am
connecting A0-A12 of processor's address bus to A0-12 of SDRAM and A13,A14
of processor to BA0,BA1 of SDRAM (alongwith other signals of read or
write).Is this way of connection true ?.
Also I want to know of any hardware or software technique by which we can
limit the size of 256Mb RAM to 128Mb or 64 Mb.
Regards,
Adeel
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