[SI-LIST] Re: SDRAM connection
- From: "Mehrdad Salami" <msalami@xxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Fri, 12 Sep 2003 10:11:49 +1000
Adeel,
It depends on SDRAM controller in your processor. If you have
controller, follow their recommendation of how to connect the external
address lines. The processor uses 23 address lines internally and
divides them to 13 for row and 10 for column. Then the processor
delivers them on external address lines based on predefined timing (for
both controller and SDRAM chip). Delivering on which external address
lines depends on the SDRAM controller. There are also three signals
which is used for commands (CAS, RAS and WE) and generated by SDRAM
controller. Most controllers also have Chip select signal.
If you don't have SDRAM controller in your processor, it would be hard
(if not impossible) to use SDRAM. You need to take care of refreshing,
changing the address lines and sending commands based on the SDRAM
clock. For such cases I recommend to use FPGA between processor and
SDRAM. Write the SDRAM controller on FPGA and processor can request data
from FPGA instead of dealing with SDRAM directly.
Cheers
Sal
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Adeel Malik
Sent: Friday, September 12, 2003 2:05 AM
To: 'si-list@xxxxxxxxxxxxx'
Subject: [SI-LIST] SDRAM connection
Hi All,
I need to connect 32M8 256Mb SDRAM to a processor. The SDRAM
has
13 Address Lines for Row Decoding (8K rows) and 10 Address lines for
column
decoding (1K columns) and two additional address lines BA0 and BA1. I am
connecting A0-A12 of processor's address bus to A0-12 of SDRAM and
A13,A14
of processor to BA0,BA1 of SDRAM (alongwith other signals of read or
write).Is this way of connection true ?.
Also I want to know of any hardware or software technique by which we
can
limit the size of 256Mb RAM to 128Mb or 64 Mb.
Regards,
Adeel
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