[SI-LIST] SATA Gen2 Simulation Validation
- From: Ned.Dempsher@xxxxxxxxxx
- To: <si-list@xxxxxxxxxxxxx>
- Date: Tue, 12 May 2009 16:25:59 -0400
Hi SI-LIST,
We are designing a SATA Gen2 board/interface.
In reading the specification it appears that the jitter is specified as
clock to data jitter for Gen2.
The spec. shows that compliance is verified by connection to a scope
that contains the proper CDR PLL so that clock to data jitter can be
measured.
In simulating my design how am I able to verify that I am close to
meeting the specification if I do not have the CDR PLL in my simulation?
The SATA device vendors do not provide any details in this regard and
neither do the silicon vendors we are using.
This is new to us here. Any advise would be greatly appreciated.
Ned Dempsher
L-3 Communications
Camden, NJ
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