[SI-LIST] Re: LVDS Buffers Connection

  • From: "Lynne D. Green" <lgreen22@xxxxxxxxxxxxxx>
  • To: "'Mohamad Haghtalab'" <mohaghtalab@xxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
  • Date: Tue, 12 May 2009 13:46:26 -0700

Mohamad, you might ask the vendor to submit the IBIS file to the IBIS Model
Review Committee.
http://www.eigroup.org/ibis/support.htm  For further info, the vendor can
contact the Chair, Lynne Green,
lgreen22@xxxxxxxxxxxxxxx

All,

Sometimes there is not enough expertise to validate an IBIS file in-house.
I have run into companies that did not run the IBIS parser before releasing
models to the design team, and the thought of running incoming QA on
models was a new concept.

If there is expertise in house, the IBIS Quality Checklist could be used to
communicate potential issues with the vendor.
http://www.vhdl.org/pub/ibis/quality_wip/

Lynne
Chair, IBIS Model Review Committee



"IBIS training when you need it, where you need it."

Dr. Lynne Green
Green Streak Programs
http://www.greenstreakprograms.com
425-788-0412
lgreen22@xxxxxxxxxxxxxx
 

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Aubrey Sparkman
Sent: Tuesday, May 12, 2009 1:11 PM
To: 'Beal, Weston'; 'Mohamad Haghtalab'; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: LVDS Buffers Connection

Weston,

You are being very kind.  My experience says that if you have no history
with a particular model source, you should assume the model you are given is
wrong until testing tells you otherwise. 


Aubrey Sparkman
Aubrey.K.Sparkman@xxxxxxxx

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Beal, Weston
Sent: Tuesday, May 12, 2009 11:13 AM
To: Mohamad Haghtalab; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: LVDS Buffers Connection

Mohamad,

This sounds like a model problem. You should not assume that your models are
correct just because a vendor put them on their web site. The general
quality of simulation models is improving, but there are still problems. I
suggest that you get an expert within your company, or a consultant, or your
EDA tool support team to evaluate your models. There are also some
combinations of models, circuits and simulators that just don't behave well
together. Your EDA tool support people can help with that, if it happens to
be the problem.

Regards,
Weston


-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Mohamad Haghtalab
Sent: Tuesday, May 12, 2009 8:52 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] LVDS Buffers Connection

Hi all
 
We have an A/D (LTC2242-10 for Linear Technology )  with LVDS outputs,the
output 
 
data are connected (via LVDS Transmission Line of Zdiff~100 and Rterm = 100
near the 
 
recievers) to FPGA (Virtex2) for data processing( both of driver and
reciever are LVDS).
 
for SI simulation we chose LVDS model for driver (with voltage range 2.5v)
and LVDS33 
 
(voltage range 3.3)for the reciever ,after this we observed that the
waveforms(in both 
 
side) were so bad,but after replacing the LVDS model of driver with LVDS33 
 
model of Virtex 2 the results changed significantly (became very good),
 
what kind of problem are we dealing with?
 
is it correct to connect two different kinds of LVDS (different voltage
range for instance or 
 
other ...)buffers together ?
 
or could be anything wrong with simulation setup?
 
if all above is correct can we conclude that these two buffers can't be
connected with 
 
currently configuration? 
 
and how can we overcome this problem?
 
Thanks for help
 
Regards
 
 
 
 
 
 
 
 
 
 
 
 
 

      
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