[SI-LIST] Re: SATA Gen2 Simulation Validation
- From: "T.K. Jeon" <tkjeon@xxxxxxxxxxx>
- To: "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
- Date: Thu, 14 May 2009 11:41:51 -0700
Hi Ned,
As far as the jitter is concerned, CDR is just a highpass filter. Thus, if you
just apply a single pole highpass filter with proper corner frequency and
peaking as stated in SATA standard, then that should be reasonably good for
your jitter measurement.
Regards,
TK
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Dave Instone
Sent: Wednesday, May 13, 2009 2:44 AM
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: SATA Gen2 Simulation Validation
Ned,
You need to make sure that you have all the ratified ECNs to the 2.6
SATA spec (it's more than 2 years old), in particular there is a
significant change to the reference clock definition and now includes a
definition of the closed loop transfer function of the PLL in ECN008
(008_SATA26_ECN_008_v1_FB500_Final.pdf), which can be obtained by down
loading the zip file of Serial ATA 2.6 Ratified Errata from the member
area of the SATA-IO web site www.sata-io.org. You may find that there
is sufficient detail to enable you to model a compliant PLL.
While your vendors silicon may not, and is not mandated, to have a PLL
with the specified CLTF etc all the jitter specifications use it. Thus
your vendors silicon cannot have a worse performance. Ie the Tx worse
case jitter must be no worse than the spec requirement when measured
using the Spec reference clock, the Rx must perform when the max allowed
jitter again measured using the Spec reference clock is applied.
Regards
Dave Instone
+44 (0)1235 824963
OXFORD SEMICONDUCTOR LIMITED
25 MILTON PARK
ABINGDON
OXFORDSHIRE
OX14 4SH
Registered in England no 2733820
Registered Address: As above
A Subsidiary of PLX Technology, Inc
Ned.Dempsher@xxxxxxxxxx wrote:
> Hi SI-LIST,
>
>
> We are designing a SATA Gen2 board/interface.
>
>
>
> In reading the specification it appears that the jitter is specified as
> clock to data jitter for Gen2.
>
> The spec. shows that compliance is verified by connection to a scope
> that contains the proper CDR PLL so that clock to data jitter can be
> measured.
>
>
>
> In simulating my design how am I able to verify that I am close to
> meeting the specification if I do not have the CDR PLL in my simulation?
>
>
>
> The SATA device vendors do not provide any details in this regard and
> neither do the silicon vendors we are using.
>
>
>
> This is new to us here. Any advise would be greatly appreciated.
>
>
>
> Ned Dempsher
>
> L-3 Communications
>
> Camden, NJ
>
>
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