[SI-LIST] Regarding Controlled Impedance
- From: "Embedded" <hw_si@xxxxxxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: 13 Oct 2009 18:56:27 -0000
Dear Experts,
In my 8-Layer design, as per stackup for 50 ohm SE impedance trace width
mentioned requirement is 12 mils for microstrip lines.
It is not possible to maintain 12 mils trace width considering my board size
and component placement density. I can use only less than 6 mils trace width
for microstrip.
So we decided to route non-critical signals in Microstrip routing.
We have identified the follwoing group of signals are not critical since their
operating frequency is less.
UART - Max baud rate 3 Mbps
SSP - Max bit rate 26Mbps
Key Pad - in KHz.
SDIO - 25 Mhz.
AS per our understanding to condider a signal trace is transmission line (high
speed signal),the critical length is important.To calculate critical length the
rise time and fall time of the signal is taken.
Thumb rule says "Regardless of the clock or data frequency the design uses, the
Effective Operating Frequency of a circuit, or trace is: Signal Frequency [GHz]
= [0.35] / [Signal Transition Time {nSec}"
But the rise time and fall time for specific interface is not mentioned in my
CPU datasheet. In datasheet commonly mentioned as Fast and Slow slew rate IOs.
The above mentioned group of signals are coming under slow slew rate IOs. The
slow slew rate mentioned as 1.6V/1nS. So rise time tr = 2.06nS for LVCMOS 3.3V
IO logic.
So my effective frequency comes around 170Mhz. Is my understanding correct?
So do we need to match impedance strictly for these signals?
Looking forward your valuable inputs.
Thanks in Advance.
MR
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