[SI-LIST] Re: Referencing multiple voltages in a stackup
- From: "Ken Cantrell" <Ken.Cantrell@xxxxxxxxxxxxxxxx>
- To: <weirsp@xxxxxxxxxx>, <chris.mcgrath@xxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Thu, 21 Oct 2004 16:49:58 -0600
Chris,
If the 1.5V plane is the core voltage for a big mega-gate FPGA, I would be
more concerned about the 1.5V noise leaking into the I/O since the core
current is significantly larger than the I/O current. I never stack them
together. I use something like
Top (sig)
Gnd
1.5V
Sig1
3.3V
Sig2
Gnd
and on down the stack.
Ken
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of steve weir
Sent: Thursday, October 21, 2004 4:01 PM
To: chris.mcgrath@xxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Referencing multiple voltages in a stackup
Chris,
You need to be very careful with that proposal. In a perfect world,
signals return only against the reference ( typically ground ) for the I/O,
and only operate on one side of that reference plane. It is not much worse
to operate on both sides of the plane. The antipad for the signal via
typically provides the return signal path from one side of the plane to the
other.
Substantively worse is the common practice of offset striplines in a Vcc
Sig Sig Gnd sandwich. Most of the return current has to work its way to
nearby decoupling capacitors on the surface and back down to the opposing
power layer. This works OK for non-demanding signals, but makes for
resonant cavities that can be vexing.
Then we get to what I understand as your proposal. Be afraid, be very
afraid. For that proposal to fly, you need to thoroughly evaluate the
effective inductance between whatever chunk of metal you are attempting to
use as an image plane and the rest of the return signal path, and be able
to show that the L*di/dt is not going to first create an EMC nightmare and
secondly will not create signaling problems. You could readily create a
situation where no amount of decoupling will make the board work.
Steve
At 02:09 PM 10/21/2004 -0700, Chris McGrath wrote:
>I'm putting together a stackup with roughly 20 layers that requires
>distribution of five different voltages and I'm wondering what effect
>running 3.3V logic (133MHz) adjacent to a lower voltage reference plane
>(such as 1.5V) would have on the lower voltage reference plane. =20
>
>I understand the concept of the power plane operating as a reference
>plane, but with 4 mil cores throughout the board, I am worried about
>coupling switching noise from 3.3V signals into lower voltage reference
>planes adjacent to the 3.3V signals. =20
>
>As I see it, the conservative approach would be to only route 3.3V
>signals next to the 3.3V plane or next to a ground plane. However,
>given the rise times involved (~ 1ns), I tend to believe that sufficient
>decoupling and stitching together of ground planes in the area would
>suppress any noise that could potentially couple into the lower voltage
>planes. My understanding is that for the higher speed signals (over 1
>GHz), it is not wise to route adjacent to any reference other than
>ground and the voltage reference for the GHZ signals. My question
>mainly revolves around signals running at less than 1 GHz.
>
>I am interested in hearing any opinions you may have on the topic. We
>often talk about stackups but I could not find anything in the archives
>that addressed the issue of stackups with a number of different
>voltages.
>
>Thanks,
>Chris
>
>
>------------------------------------------
>Chris McGrath
>Sr. Hardware Engineer
>ADIC
>ph: (607) 241-4858
>eM: chris.mcgrath@xxxxxxxx
>------------------------------------------
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