[SI-LIST] Re: Referencing multiple voltages in a stackup
- From: "Grasso, Charles" <Charles.Grasso@xxxxxxxxxxxx>
- To: "'ruston_matt@xxxxxxx'" <ruston_matt@xxxxxxx>, "'si-list@xxxxxxxxxxxxx'" <si-list@xxxxxxxxxxxxx>
- Date: Fri, 22 Oct 2004 08:30:16 -0600
Thanks Ruston,
I think the problem is the looonggg web link
in the email.
Try the RMCEMC home page
http://www.ieee.org/rmcemc and navigate from there.
Best Regards
Charles Grasso
Senior Compliance Engineer
Echostar Communications Corp.
Tel: 303-706-5467
Fax: 303-799-6222
Cell: 303-204-2974
Email: charles.grasso@xxxxxxxxxxxx;
Email Alternate: chasgrasso@xxxxxxxx
-----Original Message-----
From: ruston, matt [mailto:ruston_matt@xxxxxxx]
Sent: Friday, October 22, 2004 7:23 AM
To: 'si-list@xxxxxxxxxxxxx'
Subject: [SI-LIST] Re: Referencing multiple voltages in a stackup
Geoff, Charles:
Hi. A better link might be
http://www.ewh.ieee.org/r5/denver/rockymountainemc/archive/2004/Sep/index.ht
ml
Then click on "Download the Presentation(~4MB)"
The original link doesn't seem to work.
Regards,
Matt
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Grasso, Charles
Sent: Friday, October 22, 2004 9:08 AM
To: 'gstokes@xxxxxxxxx'; 'si-list@xxxxxxxxxxxxx'
Subject: [SI-LIST] Re: Referencing multiple voltages in a stackup
Hi Geoff,
Rest assured that the presentation will NOT disappear.
The meeting information (presentation AND pictures) will
be safely stored under our archive link.
Best Regards
Charles Grasso
Senior Compliance Engineer
Echostar Communications Corp.
Tel: 303-706-5467
Fax: 303-799-6222
Cell: 303-204-2974
Email: charles.grasso@xxxxxxxxxxxx;
Email Alternate: chasgrasso@xxxxxxxx
-----Original Message-----
From: Geoff Stokes [mailto:gstokes@xxxxxxxxx]
Sent: Friday, October 22, 2004 5:55 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Referencing multiple voltages in a stackup
Hi Jim
This link was posted here a few days ago.
http://www.ewh.ieee.org/r5/denver/rockymountainemc/archive/2004/Sep/Maxwell.
pdf
I recommend you download it in case it disappears at some point.
Page 57 says that for high frequency, ground is a concept that does not
exist. There is a fair amount of discussion to back that view. The high
frequency components of a signal return through various paths, including Vdd
plane decoupling caps and 0V plane. So basically you are right if you add
the fact that the (distributed) load current might be dumped either in the
0V or Vdd conductors/planes, whereas, as you point out in many cases it must
return to the FET drain or source. Actually the power planes are AC
"ground" planes. They carry currents and develop associated local voltage
drops and give rise to system imperfections in terms of pulse shapes and
noise immunity at critical devices. But the important point is that in
order for the return current coupling, radiation and susceptibility all to
be kept to a minimum, the immediate current-carrying parts of power and 0V
planes must be well-stitched together, using vias and decoupling caps.
Cheers
Geoff
> -----Original Message-----
> From: Peterson, James F (FL51) [mailto:james.f.peterson@xxxxxxxxxxxxx]
> Sent: 22 October 2004 12:23
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: Referencing multiple voltages in a stackup
>
>
> With regards to Chris's comments below:
> (paraphrasing : return currents reluctantly using the Vcc plane until
> they can get to a ground plane.) with a typical driver topology
> (totem pole), and
> the driver switched to a logic "1" state, don't return
> currents want to use
> this Vcc plane. Don't they need to return to the pullup FET
> (Kirchhoff's
> current law)? If this is true, it seems the return currents
> would want to
> hop on the Vccio plane to get back to that FET.....I've
> always been curious
> about this and have heard different arguments.
> thanks,
> Jim Peterson
> Honeywell
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of steve weir
> Sent: Thursday, October 21, 2004 6:01 PM
> To: chris.mcgrath@xxxxxxxx; si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: Referencing multiple voltages in a stackup
>
>
> Chris,
>
> You need to be very careful with that proposal. In a perfect world,
> signals return only against the reference ( typically ground
> ) for the I/O,
> and only operate on one side of that reference plane. It is
> not much worse
> to operate on both sides of the plane. The antipad for the
> signal via
> typically provides the return signal path from one side of
> the plane to the
> other.
>
> Substantively worse is the common practice of offset striplines in a
> Vcc Sig Sig Gnd sandwich. Most of the return current has to work
> its way to
> nearby decoupling capacitors on the surface and back down to
> the opposing
> power layer. This works OK for non-demanding signals, but makes for
> resonant cavities that can be vexing.
>
> Then we get to what I understand as your proposal. Be afraid, be very
> afraid. For that proposal to fly, you need to thoroughly evaluate the
> effective inductance between whatever chunk of metal you are
> attempting to
> use as an image plane and the rest of the return signal path,
> and be able
> to show that the L*di/dt is not going to first create an EMC
> nightmare and
> secondly will not create signaling problems. You could
> readily create a
> situation where no amount of decoupling will make the board work.
>
> Steve
> At 02:09 PM 10/21/2004 -0700, Chris McGrath wrote:
>
> >I'm putting together a stackup with roughly 20 layers that requires
> >distribution of five different voltages and I'm wondering what effect
> >running 3.3V logic (133MHz) adjacent to a lower voltage
> reference plane
> >(such as 1.5V) would have on the lower voltage reference plane. =20
> >
> >I understand the concept of the power plane operating as a reference
> >plane, but with 4 mil cores throughout the board, I am worried about
> >coupling switching noise from 3.3V signals into lower
> voltage reference
> >planes adjacent to the 3.3V signals. =20
> >
> >As I see it, the conservative approach would be to only route 3.3V
> >signals next to the 3.3V plane or next to a ground plane. However,
> >given the rise times involved (~ 1ns), I tend to believe
> that sufficient
> >decoupling and stitching together of ground planes in the area would
> >suppress any noise that could potentially couple into the
> lower voltage
> >planes. My understanding is that for the higher speed
> signals (over 1
> >GHz), it is not wise to route adjacent to any reference other than
> >ground and the voltage reference for the GHZ signals. My question
> >mainly revolves around signals running at less than 1 GHz.
> >
> >I am interested in hearing any opinions you may have on the
> topic. We
> >often talk about stackups but I could not find anything in
> the archives
> >that addressed the issue of stackups with a number of different
> >voltages.
> >
> >Thanks,
> >Chris
> >
> >
> >------------------------------------------
> >Chris McGrath
> >Sr. Hardware Engineer
> >ADIC
> >ph: (607) 241-4858
> >eM: chris.mcgrath@xxxxxxxx
> >------------------------------------------
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