[SI-LIST] Re: RX PLL bandwidth < TX PLL Bandwidth
- From: "Dhamija, Naresh" <Naresh.Dhamija@xxxxxxx>
- To: "tkjeon@xxxxxxxxxxx" <tkjeon@xxxxxxxxxxx>, "ah.vinod@xxxxxxxxx" <ah.vinod@xxxxxxxxx>, SI-LIST <si-list@xxxxxxxxxxxxx>
- Date: Fri, 8 Feb 2013 16:35:40 +0530
Rx PLL has a VCO also whose Transfer Function is high pass. So if the Rx PLL BW
is more, you will get the phase noise tracked out of VCO. So it's a trade off
between Input Transer Function (having Low Pass response) and Noise Transfer
Function of VCO ( having high pass response).
Regards
Naresh
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of T.K. Jeon
Sent: Friday, February 08, 2013 6:38 AM
To: ah.vinod@xxxxxxxxx; SI-LIST
Subject: [SI-LIST] Re: RX PLL bandwidth < TX PLL Bandwidth
Hi Vinod,
When you say "RX PLL bandwidth (CDR) is typically much smaller than ~", it
sounds like to me you are mentioning the cutoff frequency(Fc) of Rx jitter
transfer function, which shows high-pass behavior. If that is the case, Fc is
not the same as CDR BW. Indeed, Fc is pretty much the same as the unity gain BW
of the open loop TF of CDR loop. Hence, the -3dB BW of the closed loop TF is
higher than that(typically 2~3 times of Fc).
You cannot set the BW as high as you want because the phase response is the
also a critical factor for your system. In addition, it is actually the open
loop gain that attenuates the SSC, whose its frequency is way lower than the
CDR BW.
Best Regards,
TK
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of vinod ah
Sent: Tuesday, February 05, 2013 4:28 AM
To: SI-LIST
Subject: [SI-LIST] RX PLL bandwidth < TX PLL Bandwidth
HI All,
I have generic question. In many serial IO standards like USB3 or USB2 etc, RX
PLL bandwidth (CDR) is typically much smaller than the TX PLL bandwidth.
1) It is good to have smaller Tx PLL bandwidth so as to reduce the reference
clock jitter and at the same time pass the SSC if used. So what is the need for
higher Tx PLL bandwidth?
2) It is good to have higher Rx PLL bandwidth so as to track the jitter and
also pass SSC. Ideally Rx PLL bandwidth should be > than Tx PLL bandwidth so as
to completely track the Tx jitter and channel jitter, but all IO standards have
the reverse. Is there any reason for the same.
Regards
Vinod A H
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