[SI-LIST] RX PLL bandwidth < TX PLL Bandwidth
- From: vinod ah <ah.vinod@xxxxxxxxx>
- To: SI-LIST <si-list@xxxxxxxxxxxxx>
- Date: Tue, 5 Feb 2013 17:57:51 +0530
HI All,
I have generic question. In many serial IO standards like USB3 or USB2 etc,
RX PLL bandwidth (CDR) is typically much smaller than the TX PLL bandwidth.
1) It is good to have smaller Tx PLL bandwidth so as to reduce the
reference clock jitter and at the same time pass the SSC if used. So what
is the need for higher Tx PLL bandwidth?
2) It is good to have higher Rx PLL bandwidth so as to track the jitter and
also pass SSC. Ideally Rx PLL bandwidth should be > than Tx PLL bandwidth
so as to completely track the Tx jitter and channel jitter, but all IO
standards have the reverse. Is there any reason for the same.
Regards
Vinod A H
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