[SI-LIST] Re: RE：How can we get the resonance frequency and Q between
- From: Michael Greim <mgreim001@xxxxxxxxx>
- To: weirsi@xxxxxxxxxx
- Date: Mon, 3 Dec 2012 08:12:01 -0500
LIU,
OK, I'll ask. Did you ever ask why the reference
design is this way? Is it consistent with their own
design guidelines? We are all doing alot of speculating
as to why these caps are there and it simply may have
been a board design oops, reference design or not.
Like Steve said, that is a classic, intentionally designed
in (whether meant or not) oops. You can also ask
your vendor for information about the package. Worst
thing they can say is "No", and if they ask why you have
a very good answer.
-Michael.
We will either find a way or make one - Hannibal
In the middle of every difficulty lies opportunity - Al Einstein
If you think you can do something or you think
you can't, in both cases you are probably right - H Ford
If you're not getting the results you want with the
current approach, move on and try something else. - A. Fleischmann
On Sun, Dec 2, 2012 at 8:42 PM, steve weir <weirsi@xxxxxxxxxx> wrote:
> High ESR capacitors may or may not help depending on what the
> interconnect between those capacitors and the capacitance in the package
> is. In one strategic mistake, a major chip manufacturer traded Vss
> signal returns for Vdd_io pads. They overlooked that this practice made
> controlling resonance around the transition from the PCB PDN to the
> in-package PDN very difficult.
>
> If you don't know what the package looks like, measure it, or send it
> out for measurement to a capable facility such as Tom Dagostino's
> Teraspeed Labs.
>
> Steve
> On 12/2/2012 5:24 AM, luping liu wrote:
> > Hi Steve:
> >
> > Thanks,I just want to get a clean power, the questions comes from a
> ASIC vendors reference design which suggest us to use high ESR 100nF/0402
> decouple capacitors,I wonder if this chip has some trouble in control the
> anti resonance between the package and the board,that means taming just the
> PCB may be in trouble.
> >
> > Regards,
> > LIU Luping
> >
> >> Msg: #3 in digest
> >> Date: Thu, 29 Nov 2012 07:33:16 -0800
> >> From: steve weir <weirsi@xxxxxxxxxx>
> >> Subject: [SI-LIST] Re: How can we get the resonance
> >> frequency and Q between
> >>
> >> Measure S21 from a vantage point at two sides of the chip
> >> power
> >> connections. Depending on what else is on that rail
> >> you may have to
> >> perform multiple measurements in multiple locations in order
> >> to isolate
> >> what is due to that chip. There are various techniques to
> >> derive
> >> estimates of what is under the chip's hood by making
> >> multiple
> >> measurements. You may find some of them are on
> >> Istvan's site. If you
> >> are just trying to deliver clean power to the chip, finding
> >> and taming
> >> the PCB => package cap / die cap resonance s/b good
> >> enough. If you are
> >> trying to reverse engineer a chip, then you have more work
> >> to do.
> >>
> >> Steve.
> >> On 11/29/2012 6:54 AM, luping liu wrote:
> >>> Dear Experts:
> >>>
> >>> If we have a board with
> >> a "blackbox" chip,which means we know nothing about the
> >> package and the die details, how can we get the
> >> anti-resonance frequency and Q between the package and the
> >> board ? The measurement we can do is the Z11 looking from
> >> the PCB (with the BGA chip mounted or a bare board with
> >> decouple capacitor) with a two port VNA test.Is it possible
> >> to get the Cpackage and Cdie?
> >>> Thanks and Regards,
> >>>
> >>> LIU Luping
> >>>
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> >> --
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> --
> Steve Weir
> IPBLOX, LLC
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