[SI-LIST] RE：How can we get the resonance frequency and Q between
- From: luping liu <liewluping@xxxxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx, weirsi@xxxxxxxxxx
- Date: Sun, 2 Dec 2012 21:24:24 +0800 (CST)
Hi Steve:
Thanks,I just want to get a clean power, the questions comes from a ASIC
vendors reference design which suggest us to use high ESR 100nF/0402 decouple
capacitors,I wonder if this chip has some trouble in control the anti resonance
between the package and the board,that means taming just the PCB may be in
trouble.
Regards,
LIU Luping
>
> Msg: #3 in digest
> Date: Thu, 29 Nov 2012 07:33:16 -0800
> From: steve weir <weirsi@xxxxxxxxxx>
> Subject: [SI-LIST] Re: How can we get the resonance
> frequency and Q between
>
> Measure S21 from a vantage point at two sides of the chip
> power
> connections. Depending on what else is on that rail
> you may have to
> perform multiple measurements in multiple locations in order
> to isolate
> what is due to that chip. There are various techniques to
> derive
> estimates of what is under the chip's hood by making
> multiple
> measurements. You may find some of them are on
> Istvan's site. If you
> are just trying to deliver clean power to the chip, finding
> and taming
> the PCB => package cap / die cap resonance s/b good
> enough. If you are
> trying to reverse engineer a chip, then you have more work
> to do.
>
> Steve.
> On 11/29/2012 6:54 AM, luping liu wrote:
> > Dear Experts:
> >
> > If we have a board with
> a "blackbox" chip,which means we know nothing about the
> package and the die details, how can we get the
> anti-resonance frequency and Q between the package and the
> board ? The measurement we can do is the Z11 looking from
> the PCB (with the BGA chip mounted or a bare board with
> decouple capacitor) with a two port VNA test.Is it possible
> to get the Cpackage and Cdie?
> >
> > Thanks and Regards,
> >
> > LIU Luping
> >
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>
> --
> Steve Weir
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