[SI-LIST] Re: Question regarding current loop
- From: <steven.d.corey@xxxxxxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Fri, 28 Apr 2006 17:49:49 -0700
Hi Larry -- the lexicon is not for sale -- it is only available in the
piecemeal form of my unsolicited opinions. 8^)
The technical term for taking appropriate shortcuts when working with
circuits that are small compared to wavelength is "quasi-static
approximation". In this regime you assume that the time derivatives in
Maxwell's equations are small compared to the spatial terms, which
allows for reduced order solutions. This is essentially the same as the
oft-cited rule of thumb that rise time should be less than 1/6 the
electrical length of what you're modeling. In this regime, you can
generally get away with a single L and/or C to represent the reactance
of your device.
We often call it the "lumped element regime" -- not as precise
technically, but easier to digest.
The reason I say circuit theory has been patiently waiting for digital
design to find its way into the full-wave arena is that there are plenty
of circuit theory books (probably not targeted at EE101) from the 50's
and 60's that treat full-wave concepts, but I think this was
de-emphasized in curriculum as digital design became big. Digital
design is now being dragged into the full-wave arena, and not without
some trauma. I'll be the first to admit that when I took my
undergraduate EM courses, EM seemed fine for designing antennas, but
quite unnecessary for designing digital circuits. In fact, it seemed
scandalous when a professor predicted that some day... interconnect
delay would dominate over gate delay.
-- Steve
------------------------------------------------------------------------
-
Steven D. Corey, Ph.D.
Principal Engineer
Tektronix - Enabling Innovation
=20
http://www.tdasystems.com
http://www.tektronix.com
=20
email: steven.corey@xxxxxxxxxxxxx
phone: (503) 627-6816
fax: (503) 627-2260
------------------------------------------------------------------------
-
=20
>-----Original Message-----
>From: Larry Smith [mailto:LSMITH@xxxxxxxxxx]=20
>Sent: Friday, April 28, 2006 9:47 AM
>To: Corey, Steven D; si-list@xxxxxxxxxxxxx
>Subject: RE: [SI-LIST] Re: Question regarding current loop
>
>Steve - Yes, this is just semantics, perhaps I need to get a copy of
>your lexicon. :) Over the years I believe we have expanded our
>definition of "circuit theory" because the field concepts are just too
>difficult to deal with.
>
>At audio frequencies, there is no need to use field theory or=20
>time delay
>concepts. I can analyze the signals at my speakers without ever
>thinking about t-lines. Remember the 8MHz microprocessors? The TTL
>circuits probably had a 5 nSec rise time and all you needed to know was
>the output resistance (or current) and the load capacitance to analyze
>timing. Trace length was not an issue unless it added=20
>significant R and
>C. =20
>
>We have plenty of good high speed circuit designers that deal with
>internal logic circuits and even I/O drivers and receivers on chip. If
>I talk to them about ports and S parameters there eyes will roll and
>communications will have broken down. I have been asked the meaning of
>the TDR and VNA acronyms as if they hold the keys to deep dark secrets.
>Multi port scattering parameters are not in their vocabulary but they
>are world class circuit designers in the transistor world. =20
>
>What do these things have in common? They are all examples of circuits
>with physical size less than 1/20th of a wavelength of the highest
>frequency of interest. And, yes you can assume that a trace=20
>is a single
>node with no time delay if it short enough compared to a=20
>wavelength. We
>certainly don't use transmission lines to represent the trace that goes
>from one transistor to another. (Well, maybe if we are going a
>significant distance across the die, but then it is an RC t-line.. And
>yes, on-chip signal integrity is becoming an issue.).
>
>Back in the dark ages when I went to school, EE101 involved circuits
>with RLC & G's and some voltage and current sources. In our sophomore
>year we took the bran new transistor class that the profs were
>struggling with because it replaced the vacuum tube class that had been
>dropped from the previous year. Transmission lines were introduced in
>our junior year after we had some field theory. Perhaps my definition
>of circuit theory is a bit different than yours. Things have changed
>for the better.. =20
>
>The discussion that was going on between Scott and Doug seemed to be
>based on language of field theory and circuit theory (the archaic
>definition of the word). Does your lexicon have a word or phrase for
>analysis of circuits that are less than 1/20th of a wavelength?
>
>Regards,
>Larry Smith
>Altera Corporation
>
>PS - From your definition of "circuit theory" it seems that the only
>place you can talk about voltage and current is at a port. Yes, that
>seems like a good way to look at it. My, how things have changed. :)
>
>-----Original Message-----
>From: si-list-bounce@xxxxxxxxxxxxx=20
>[mailto:si-list-bounce@xxxxxxxxxxxxx]
>On Behalf Of steven.d.corey@xxxxxxxxxxxxxx
>Sent: Thursday, April 27, 2006 6:32 PM
>To: si-list@xxxxxxxxxxxxx
>Subject: [SI-LIST] Re: Question regarding current loop
>
>Hi Larry -- this may seem like pure semantics, but I would=20
>disagree with
>your characterization of circuit theory. In my lexicon, circuit theory
>describes system behavior in terms of what have traditionally been
>called "circuit variables" (e.g., voltage, current, voltage=20
>waves, power
>waves). I suppose field theory could analogously describe system
>behavior in terms of its "field variables" (e.g., E,H fields).
>Basically, field variables are defined at points, and circuit variables
>are defined at ports.
>
>In this sense, circuit theory encompasses concepts such as multiport
>scattering parameters -- they're just a transformed version of=20
>impedance
>or admittance parameters, which actually were covered in=20
>EE101. It also
>includes delay between ports -- an example might be T-Line equations
>relating circuit variables voltage and current (or even incident and
>reflected voltage waves) at the ports of a T-Line network. PEEC
>modeling is an example of a method that maps field interactions into
>circuit variables without loss of generality.
>
>Clearly you can't assume that a signal trace is a single circuit node
>with zero delay. Nor would I advocate the charge-hose concept of a
>posse of electrons running full tilt down a transmission line, climbing
>down to the ground plane, and hot-footing it back home. It's also been
>pointed out in the past on this list that you can't expect to measure a
>unique voltage between two points several wavelengths apart. None of
>these is an inherent shortcoming of circuit theory, but each is an
>example of misapplication of circuit theory in a high-speed=20
>environment.
>
>You definitely need to understand the fields and their interactions to
>be able to build a reliable high-speed circuit that is a good neighbor
>in the FCC sense. You may even use a field solver to figure out the
>port behavior of part of your circuit. But at the end of the day you
>have to present a certain voltage to the input port of your receiver,
>complete with enough current to charge or discharge its input=20
>circuitry.
>In other words, we're stuck with circuit theory... Rather than
>discarding it, I would say that we're actually learning better what it
>is and how to use it for high-speed design.
>
> -- Steve
>
>---------------------------------------------------------------
>---------
>-
>Steven D. Corey, Ph.D.
>Principal Engineer
>Tektronix - Enabling Innovation
>=3D20
>http://www.tdasystems.com
>http://www.tektronix.com
>=3D20
>email: steven.corey@xxxxxxxxxxxxx
>phone: (503) 627-6816
>fax: (503) 627-2260
>---------------------------------------------------------------
>---------
>-
>=3D20
>
>>-----Original Message-----
>>From: si-list-bounce@xxxxxxxxxxxxx=3D20
>>[mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of Larry Smith
>>Sent: Thursday, April 27, 2006 12:24 PM
>>To: scott@xxxxxxxxxxxxx; doug@xxxxxxxxxx
>>Cc: si-list@xxxxxxxxxxxxx
>>Subject: [SI-LIST] Re: Question regarding current loop
>>
>>Scott - Your recent post was really interesting, I enjoyed reading it.
>>Thanks for taking the time to write it up. I think that what we are
>>discussing here is the field theory view of the world and the circuit
>>theory view of the world.=20
>>
>>In circuit theory, Kirchhoff has given us laws that discuss loop
>>voltages and branch currents (EE101). There is no concept of time
>>across a node. With low speed signals, the near and far ends=20
>of traces
>>are connected with copper and considered to be the same node.=20
>>Simple RC
>>time constants can be used to evaluate the time delay from driver to
>>receiver. (That is so 1980's... S parameters need not apply.) Never
>>the less, these are the circuit theory concepts that we use in
>>evaluating local circuits where there is not a significant
>>time delay in
>>the physical size of the circuit.
>>
>>The concepts in your post are based on field theory. A trace is not a
>>node but a transmission line delay element, or else a string of nodes
>>separated by L's and C's with equations like v=3DL*di/dt and
>>i=3DC*dv/dt .
>>Circuit theory still works but it is running out of gas and concepts
>>break down.
>>
>>The dividing line between circuit theory and field theory is when the
>>length of the trace becomes a significant portion of the rise time. A
>>good rule of thumb for this dividing line would allow the
>>trace to be no
>>longer than 1/3 of a rise time for data lines, 1/5 of a rise time for
>>clock signals and 1/7 of a rise time for instrumentation. =20
>That way the
>>near end will have a chance to influence the far end 2, 3 and 4 times
>>during the rise time respectively. Using the relationships
>>freq=3D0.35/t_rise and period=3D1/frequency, we find that
>>trace may be
>>1/8.6, 1/14.3 and 1/20 of a wavelength for data, clocks and
>>instruments,
>>listed in order of increasing accuracy requirements.=20
>>
>>When the physical size of the circuit (trace length) becomes more than
>>1/20th of a wavelength long, simple circuit theory (charge
>>hose analogy)
>>begins to break down and you must use field theory concepts to
>>understand what is happening.=20
>>
>>It is kind of interesting that you can start with the=20
>concepts (1) that
>>1/20th of a wavelength is where circuit size becomes important=3D20
>>and (2) a
>>trace becomes a transmission line when it is more than 1/7th of a rise
>>time long and then work backwards to find that frequency content is
>>0.35/t_rise. It's just another interesting way of looking at this.
>>
>>Regards,
>>Larry Smith
>>Altera Corporation
>>
>>
>>
>>
>>
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