Heidi,
Good seeing to today at EDICON. Here's my take on the terms.
As an editor, I tend to define a term and stick with it for consistency. For
example, when I was at Test & Measurement World, we had a specific use for the
acronym ATE (automatic test equipment). We used it when referring to the "big
iron" semiconductor testers from Teradyne, HP/Agilent/Verigy, Advantest, LTX,
and others. But, people who built automated test systems out of box or modular
instruments, usually for functional test, also used ATE. You can still hear
both at conferences such as ITC for semiconductor test and Autotestcon for
military functional test.
I think of "Power Integrity" relating to DC power distribution on high speed
digital boards. There are other terms and other applications where power
integrity could apply. For example, AC mains power. But there, I would say
"power quality" when speaking of dips, harmonics, and interruptions of AC
power. In that world, suppose a system or piece of machinery needs power
quickly, say on startup. The current surge could cause a dip in AC power,
perhaps in a room, building, or AC power circuit. Yes, it's due to impedance
in the AC wiring. For example, my old laser printer would cause the room lights
to flicker when printing as they were on the same circuit. I would also use the
term "power quality" should some device add interference to other devices on
the same circuit in the form of harmonics. I often hear "power quality" used by
EMC engineers.
Now, what about DC power distribution in power electronics, analog, RF, or
lower speed digital circuits? I don't know of a term for those DC power issues.
Perhaps "power fidelity" could be used.
I've heard "signal fidelity" used, but more so as a substitute for signal
integrity.
Martin Rowe
Senior Technical Editor, Test & Measurement
1-212-600-3403
martin.rowe@xxxxxxxxxxxxx as of August 1, 2016
EDN Test & Measurement Design Center
EE Times Test & Measurement DesignLine
@measurementblue
@TMW_Community
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On ;
Behalf Of heidi_barnes@xxxxxxxxxxxx
Sent: Monday, September 19, 2016 8:37 PM
To: leeritchey@xxxxxxxxxxxxx; larrys@xxxxxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Power Integrity meets Power Electronics in the Midwest
Larry,
I agree completely, and I especially like the last statement about managing PDN
impedance in all frequency bands, time zones, and levels of assembly.
However, there is still a lot of industry education required. It reminds me
of the SI transition from the days of analog "charging capacitance" on high
speed data lines to transmission line theory.
Thanks for chiming in on my PI question.
-Heidi
-----Original Message-----
From: Lee Ritchey [mailto:leeritchey@xxxxxxxxxxxxx] ;
Sent: Monday, September 19, 2016 3:46 PM
To: larrys@xxxxxxxxxxxxxxxx; BARNES,HEIDI (K-SantaRosa,ex1)
<heidi_barnes@xxxxxxxxxxxx>; si-list@xxxxxxxxxxxxx
Subject: RE: [SI-LIST] Re: Power Integrity meets Power Electronics in the
Midwest
Well said!
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On ;
Behalf Of Smith, Larry
Sent: Monday, September 19, 2016 3:22 PM
To: heidi_barnes@xxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Power Integrity meets Power Electronics in the Midwest
Heidi - In my mind, the power integrity problem is "DC to daylight." We
need to concern ourselves with everything from seconds to pico-seconds, which
is more than 10 decades of frequency content.
Power integrity engineers in the mobile space are vitally concerned about
battery life and protection of the battery from over-current. In the server
space we are concerned with power consumption from the building and public
utility grid. We are concerned with VRMs including the SMPS (switched mode
power supply, buck converters) and the LDO (low drop out, linear regulators)
and their interface to bulk capacitors on the board. We are concerned with the
high-frequency ceramic capacitors and their mount to the board power planes.
Likewise, the electronic package, package caps, vias and package power planes.
Then there are the die bumps, on-die power grid in 10 layers of metal, vias and
on-die capacitance.
We are concerned with clock edge noise in a small portion of a 2 GHz clock
cycle (500 pSec period) as well as the VRM droop that lasts for micro-seconds
(1000's of clock cycles) and sufficiently low battery impedance to support
maximum loading.
It really all comes down to managing your PDN impedance in all frequency bands,
time zones and levels of assembly.
Regards,
Larry Smith
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On ;
Behalf Of heidi_barnes@xxxxxxxxxxxx
Sent: Monday, September 19, 2016 10:40 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Power Integrity meets Power Electronics in the Midwest
To All:
I have a question for the SI world now that PI is rapidly catching on to the
world of high frequencies.
Does Power Integrity include Power Electronics and Power Distribution
Networks... or does it only apply to powering high speed digital devices?
Next week I will be co-presenting with my colleague Chris Mueth. I will be
covering the latest in Power Integrity, and Chris Mueth on Power Electronics at
three stops in the Midwest:
September 27th - Bloomington, Mn (Minneapolis) September 28th - Schaumburg, IL
(Chicago) September 29th - Novi, MI (Detroit) (Special guest Steve Sandler of
Picotest, author of Power Integrity)
If you are interested, please check out the link or send me a reply:
http://www.keysight.com/main/eventDetail.jspx?cc=US&lc=eng&ckey'26153&nid=-3
5198.0.08&id'26153
At our final stop in Detroit, industry expert Steve Sandler of Picotest and
author of the book Power Integrity: Measuring, Optimizing, and Troubleshooting
Power Related Parameters in Electronics Systems will be a guest speaker. He
always welcomes questions from the audience, and I am sure he will have an
answer for my PI/PE/PDN question.
Best Regards,
Heidi Barnes
Keysight Technologies, EEsof EDA Software
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