Abe - yes, there is a simple formula for the Bandini Mountain Frequency. The
major PDN impedance peak is at f0 = 1/(2*pi*sqrt(LC)). C is the on-die
capacitance and L is the bump loop inductance. The bump loop inductance is the
inductance seen looking out through the package bumps to the mounted board
capacitors.
There is an equally useful formula for the characteristic impedance of Bandini
Mountain. It is Z0 = sqrt(L/C). The PDN voltage droop from a fast step
current is found from Z0. V_step_droop = Z0 * I_step. This is the PDN step
response.
These are two of the most important formulas that characterize the major PDN
resonant peak.
regards,
Larry Smith
________________________________
From: Abe Riazi <riaziabe@xxxxxxxxx>
Sent: Friday, July 28, 2017 6:58:27 PM
To: Larry Smith
Cc: si-list; ArunKumar.K@xxxxxxxxxxxxxxxxxxx; arunka97@xxxxxxxxx
Subject: Re: [SI-LIST] Re: Plane impedence and Target impedence
Hi Larry,
Is there a mathematical formula for computing the "Bandini Mountain Frequency",
mentioned in your email?
Thank you in advance for your response.
Abe
On Fri, Jul 28, 2017 at 10:52 AM, Larry Smith
<larry.smith@xxxxxxxxxxxxxxxxxxxxx<mailto:larry.smith@xxxxxxxxxxxxxxxxxxxxx>>
wrote:
Arun - the on-die capacitance determines the PDN impedance above a certain
frequency. This frequency is almost certainly below 800 MHz. It is the
frequency where the inductive board impedance crosses the on-die capacitance
impedance.
Most products have a frequency band where the PDN impedance exceeds target
impedance even after the on-die capacitance is considered. It seems that for
you, this starts at 75 MHz. Exceeding the target impedance represents PDN risk
but it is often too expensive to fix it. Some of us call this PDN impedance
peak "Bandini Mountain."
The important questions then become: How much transient current do we have at
Bandini Mountain frequency? How much PDN noise will the circuits tolerate in
this frequency band? These are often difficult questions with no easy answers.
For DDR, it will be signal pattern dependent.
regards,
Larry Smith
________________________________
From: si-list-bounce@xxxxxxxxxxxxx<mailto:si-list-bounce@xxxxxxxxxxxxx>
<si-list-bounce@xxxxxxxxxxxxx<mailto:si-list-bounce@xxxxxxxxxxxxx>> on behalf
of Arun Kumar K <ArunKumar.K@xxxxxxxxxxxxxxxxxxx>
Sent: Tuesday, July 25, 2017 10:30:51 PM
To: si-list
Cc: arunka97@xxxxxxxxx<mailto:arunka97@xxxxxxxxx>
Subject: [SI-LIST] Plane impedence and Target impedence
Hi Experts,
I am small doubt in Power integrity.
I did the power integrity one of the baord which is having DDR3 which will work
at 800MTps.
But all power, related to DDR are crossing the target impedence around 75MHz.
Is this necessary to keep the plane impedence under the target impedence up to
800MHz?
If yes ->, if not -> why?
Thanks & Regards
Arunkumar K
L&T Technology Services Ltd
www.LntTechservices.com<http://www.LntTechservices.com><http://www.lnttechservices.com/<http://www.LntTechservices.com<http://www.lnttechservices.com/>>
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