[SI-LIST] Plane impedence and Target impedence

  • From: Arun Kumar K <ArunKumar.K@xxxxxxxxxxxxxxxxxxx>
  • To: si-list <si-list@xxxxxxxxxxxxx>
  • Date: Wed, 26 Jul 2017 05:30:51 +0000

Hi Experts,
I am small doubt in Power integrity.
I did the power integrity one of the baord which is having DDR3 which will work 
at 800MTps.
But all power, related to DDR are crossing the target impedence around 75MHz.

Is this necessary to keep the plane impedence under the target impedence up to 
800MHz?
If yes ->, if not -> why?



Thanks & Regards
Arunkumar K



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