[SI-LIST] Placing of DDR3 chips on top and bottom sides of the PCB in a single rank system
- From: Edward Anto <edwardanto@xxxxxxxxx>
- To: "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
- Date: Thu, 12 Dec 2013 10:29:08 +0530
Hi,
My processor has got a 32-bit memory controller. I am connecting two x16
DDR3 chips in fly-by topology in single rank, both on the top side of the
PCB. I want to use a third x16DDR3 chip for connecting to four ECC lines
provided by my memory controller. But due to space constraints, I cannot
place it on the top side of the board. I need to place it on the bottom
side exactly behind one of the data DDR3 chips.
I am hoping I can find enough space on the board under the chips to
accommodate the extra vias needed for ECC data lines and strobe.
Also I am planning to share the clock, address and command vias for the top
and bottom DDR3 chips.
1. Is such a placement and connection recommended?
2. If it is possible, can address mirroring be done on the top and bottom
chips?
3. Since top and bottom chips share the same clock, address and command
vias, I believe they cannot be in fly-by. How do I take care of write
leveling then? Can I choose not to use write leveling at all, since there
are only three chips and the delay won't be considerable ?
Regards,
Edward Anto A
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List forum is accessible at:
http://tech.groups.yahoo.com/group/si-list
List archives are viewable at:
//www.freelists.org/archives/si-list
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
Other related posts:
