Thanks Ramesh. I understand the basic mistake in my previous mail. Clock, address and command cannot be length matched in fly-by. If I wish not to use write leveling feature in fly-by topology, I should be adjusting DQS lengths to each DRAM to compensate for the clock delay. Thanks for pointing that out. Regards, Edward Anto A On Thu, Dec 12, 2013 at 3:16 PM, Ramesh Natesh <rameshnatesh@xxxxxxxxx>wrote: > I think CMD flight times from controller to each of the DDR3 Chips cannot > be same IF its a "fly-by". However, you can keep within tDSS, tDSH and > tDQSS by adjusting for the DQS length for each DRAM to account for the > fly-by clock. > > > > On Thu, Dec 12, 2013 at 2:23 PM, Edward Anto <edwardanto@xxxxxxxxx> wrote: > >> Thank you Hermann and Nitin. I will go ahead with the placement as >> described in my previous mail. >> Also while routing, I will make sure that the routing lengths of clock, >> command and address lines to all the three DDR3 chips be matched. So there >> won't be any timing skews among any of the chips. I don't have to worry >> about the write leveling then. >> >> Regards, >> Edward Anto A >> >> >> On Thu, Dec 12, 2013 at 11:18 AM, Bhagwath, Nitin < >> Nitin_Bhagwath@xxxxxxxxxx >> > wrote: >> >> > Hello Edward, >> > >> > Address mirroring is usually used on DIMMs to mirror entire ranks - not >> to >> > mirror DRAMs within a rank. >> > >> > Also, write leveling and fly-by is more critical for larger layouts such >> > as those found in server DIMMs. For your embedded application with >> tight >> > placement, you might be ok without using write leveling. You'll need to >> > making sure that the address/command lines are matched across the DRAMs >> and >> > also that the strobes are matched with the CLK to make sure that the >> tDSS, >> > tDSH and tDQSS times are met at the DRAMs. >> > >> > Since it doesn't sound like you'll have a symmetrical setup, and >> > especially if you're running at one of the higher frequencies, you might >> > want to simulate your setup. Hyperlynx has a "DDR Wizard" tool which >> you >> > might find useful to validate your layout. There are other >> > industry-standard simulation tools available as well which would help >> you >> > make sure that the DRAMs' and controller's timing numbers are being met. >> > >> > Best Regards, >> > -Nitin >> > ________________________________________ >> > From: si-list-bounce@xxxxxxxxxxxxx [si-list-bounce@xxxxxxxxxxxxx] on >> > behalf of Edward Anto [edwardanto@xxxxxxxxx] >> > Sent: Wednesday, December 11, 2013 8:59 PM >> > To: si-list@xxxxxxxxxxxxx >> > Subject: [SI-LIST] Placing of DDR3 chips on top and bottom sides of the >> > PCB in a single rank system >> > >> > Hi, >> > My processor has got a 32-bit memory controller. I am connecting two x16 >> > DDR3 chips in fly-by topology in single rank, both on the top side of >> the >> > PCB. I want to use a third x16DDR3 chip for connecting to four ECC lines >> > provided by my memory controller. But due to space constraints, I cannot >> > place it on the top side of the board. I need to place it on the bottom >> > side exactly behind one of the data DDR3 chips. >> > >> > I am hoping I can find enough space on the board under the chips to >> > accommodate the extra vias needed for ECC data lines and strobe. >> > Also I am planning to share the clock, address and command vias for the >> top >> > and bottom DDR3 chips. >> > >> > 1. Is such a placement and connection recommended? >> > >> > 2. If it is possible, can address mirroring be done on the top and >> bottom >> > chips? >> > >> > 3. Since top and bottom chips share the same clock, address and command >> > vias, I believe they cannot be in fly-by. How do I take care of write >> > leveling then? Can I choose not to use write leveling at all, since >> there >> > are only three chips and the delay won't be considerable ? >> > >> > Regards, >> > >> > Edward Anto A >> > >> > >> > ------------------------------------------------------------------ >> > To unsubscribe from si-list: >> > si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field >> > >> > or to administer your membership from a web page, go to: >> > //www.freelists.org/webpage/si-list >> > >> > For help: >> > si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field >> > >> > >> > List forum is accessible at: >> > http://tech.groups.yahoo.com/group/si-list >> > >> > List archives are viewable at: >> > //www.freelists.org/archives/si-list >> > >> > Old (prior to June 6, 2001) list archives are viewable at: >> > http://www.qsl.net/wb6tpu >> > >> > >> > >> >> >> ------------------------------------------------------------------ >> To unsubscribe from si-list: >> si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field >> >> or to administer your membership from a web page, go to: >> //www.freelists.org/webpage/si-list >> >> For help: >> si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field >> >> >> List forum is accessible at: >> http://tech.groups.yahoo.com/group/si-list >> >> List archives are viewable at: >> //www.freelists.org/archives/si-list >> >> Old (prior to June 6, 2001) list archives are viewable at: >> http://www.qsl.net/wb6tpu >> >> >> > > > -- > -best regards, > Ramesh Natesh > +91 9886284671 > (rameshnatesh@xxxxxxxxx) > ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List forum is accessible at: http://tech.groups.yahoo.com/group/si-list List archives are viewable at: //www.freelists.org/archives/si-list Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu