[SI-LIST] Re: Placing of DDR3 chips on top and bottom sides of the PCB in a single rank system
- From: Hermann Ruckerbauer <Hermann.Ruckerbauer@xxxxxxxxxxxxx>
- To: edwardanto@xxxxxxxxx, "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
- Date: Thu, 12 Dec 2013 06:47:00 +0100
Hello Edward,
1) yes you can do such a placement
2) no, address mirroring is not possible (it requres that the mirrored
DRAMs use a different CS).
3) This topology is still called flyby, even if two Bytes will have the
same DQ length. For all controllers I know the delay of the different
bytes does have no restriction (means each byte can be the first, the
last or do have the same delay).
Best regards
Hermann
EKH - EyeKnowHow
Hermann Ruckerbauer
www.EyeKnowHow.de
Hermann.Ruckerbauer@xxxxxxxxxxxxx
Itzlinger Strasse 21a
94469 Deggendorf
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schrieb Edward Anto:
> Hi,
> My processor has got a 32-bit memory controller. I am connecting two x16
> DDR3 chips in fly-by topology in single rank, both on the top side of the
> PCB. I want to use a third x16DDR3 chip for connecting to four ECC lines
> provided by my memory controller. But due to space constraints, I cannot
> place it on the top side of the board. I need to place it on the bottom
> side exactly behind one of the data DDR3 chips.
>
> I am hoping I can find enough space on the board under the chips to
> accommodate the extra vias needed for ECC data lines and strobe.
> Also I am planning to share the clock, address and command vias for the top
> and bottom DDR3 chips.
>
> 1. Is such a placement and connection recommended?
>
> 2. If it is possible, can address mirroring be done on the top and bottom
> chips?
>
> 3. Since top and bottom chips share the same clock, address and command
> vias, I believe they cannot be in fly-by. How do I take care of write
> leveling then? Can I choose not to use write leveling at all, since there
> are only three chips and the delay won't be considerable ?
>
> Regards,
>
> Edward Anto A
>
>
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