[SI-LIST] Re: Package Geometries.

  • From: Jory McKinley <jory_mckinley@xxxxxxxxx>
  • To: Surita Chandani <surita.chandani@xxxxxxxxx>, si-list@xxxxxxxxxxxxx
  • Date: Thu, 27 Jan 2011 12:29:19 -0800 (PST)

Layer count on board compared to package really do not correlate well.  What 
are 
you designing?
-Jory





________________________________
From: Surita Chandani <surita.chandani@xxxxxxxxx>
To: si-list@xxxxxxxxxxxxx; Jory McKinley <jory_mckinley@xxxxxxxxx>
Sent: Thu, January 27, 2011 2:32:08 PM
Subject: [SI-LIST] Re: Package Geometries.

Hello Jory,

Thanks a lot Jory for your response. You mentioned you can put only one trace 
between the bumps. On the PCB, you can easily route two traces between the 
balls, does it mean that it takes nearly twice as many layers on the package 
than the PCB for the breakout?

--- On Thu, 1/27/11, Jory McKinley <jory_mckinley@xxxxxxxxx> wrote:

> From: Jory McKinley <jory_mckinley@xxxxxxxxx>
> Subject: [SI-LIST] Re: Package Geometries.
> To: "Surita Chandani" <surita.chandani@xxxxxxxxx>, si-list@xxxxxxxxxxxxx
> Date: Thursday, January 27, 2011, 6:38 PM
> Well roughly looking at 40mmx40mm for
> your typical pin out.  Depending on your 
> impedance target your z-direction stack will be something
> like build-core-build 
> with the build layers for signals which are typically in
> the 30-40um height with 
> about 15um of trace thickness.  For 50ohms roughly
> 25um trace width.  Vias are 
> typically 20-30um radius, 100um pad or so with center to
> center of 400um to 
> 500um.  Looking at about a 1mm pitch on the Ball side
> and usually only 1 trace 
> trough a typical bump field.
> -Jory
> 
> 
> 
> 
> 
> ________________________________
> From: Surita Chandani <surita.chandani@xxxxxxxxx>
> To: si-list@xxxxxxxxxxxxx
> Sent: Thu, January 27, 2011 1:22:25 PM
> Subject: [SI-LIST] Package Geometries.
> 
> Hello Gurus;
> 
> Trying to get a general idea of package buildup and
> geometries. If I imagine a 
> package as a miniaturized PCB, I would expect all
> geometries to shrink.
> 
> For a state of the art, 1500 pin, FCBGA, what are typical
> numbers for:
> 
> 1. Trace width.
> 
> 2. Via, pad, antipad diameters.
> 
> 3. C4 Bump pitch.
> 
> 4. For the bump breakout, how many traces can you put
> between the traces.
> 
> 
> 
> 
>       
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