[SI-LIST] Re: DDR3 tQH spec.
- From: "Istvan Nagy" <buenos@xxxxxxxxxxx>
- To: "John Ellis" <John.Ellis@xxxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Thu, 27 Jan 2011 21:47:21 -0000
Hi
These parameters tell the worst case early data transitions. tQHS tells how
much earlier, while tQH tells how much after the previous DQS edge. The
distance between a DQS edge and the previous one is obviously effected by
the DCD. We can call it earliear and actual edge, or actual and next DQS
edges.
In the book "Timing Analysis and Simulation for Signal Integrity Engineers"
page-142, the tQHS was measured from an early data (to invalid state)
transition to the following DQS transition.
The DDR2 specs say this:
"tQHS accounts for:
1) The pulse duration distortion of on-chip clock circuits; and
2) The worst case push-out of DQS on one transition followed by the worst
case pull-in of DQ on the next transition, both of which are, separately,
due to data pin skew and output pattern effects, and p-channel to n-channel
variation of the output drivers. "
so, its DCD + DQ-DQS skew when the data goes invalid.
in jesd79-3e figure 27, tQHS seems to be the same after a short DQS pulse
and after a long one, not depending on DCD.
Its strange that they specify skew as x*tCK, when the clock frequency can be
changed in a running board, while the delay-related skew will not be
effected. Unless they mean that the hold-skew is happening relative to the
next clock edge, so for exmple increasing the clock period will push both
the DQ and the DQS transitions into later in time, while their relative
position (the actual delay skew) doesnt change.
For example for DDR3-800, the specified tQH=0.38*tCK would say that the
earliest data transitions maximum tCK*(0.5-0.38)=150ps before the next DQS
edge. The 0.5 is because its double data rate. They also say that
tDQSQ=200ps which is a similar value to the calculated 150ps. They also say
that the tQH (150ps) is specified as minimum, tDQSQ (200ps) as maximum
value. The delay-related skew should have the same effect at both
valid-to-invalid and invalid-to-valid transitions on the DQ bus. So i think
DCD is not taken into account for tQH, so you have to do it in your timing
budget.
regards,
Istvan Nagy
-----Original Message-----
From: John Ellis
Sent: Thursday, January 27, 2011 7:20 PM
To: Istvan Nagy ; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: DDR3 tQH spec.
Hi Istvan,
In DDR3, there is no tQHS nor tHP defined by JEDEC. These are in DDR2. The
data valid window in DDR3 is defined by the output skew tDQSQ and tQH. Both
of these are measured from the same clock edge. Both of these values are
specific numbers with tQH being 38% of the average clock period.
The implication is that for DDR3 you don't need duty cycle distortion to
determine the data valid window. From there I'm led to assume that the 38%
was determined to account for the 47/53 DCD.
That's a lot of inference and assumption. I'm curious if anybody knows
whether I'm correct.
John Ellis
Sr. Staff R&D Engineer
Mixed Signals &
I/O Libraries Group
Synopsys, Inc.
email: jellis@xxxxxxxxxxxx
Phone: 508.263.8194
-----Original Message-----
From: Istvan Nagy [mailto:buenos@xxxxxxxxxxx]
Sent: Thursday, January 27, 2011 1:36 PM
To: John Ellis; si-list@xxxxxxxxxxxxx
Subject: Re: [SI-LIST] DDR3 tQH spec.
Hi
I think it works this way, maybe I'm wrong:
Actually the DDR2 tQHS specification is unrelated to the clock period, and
the DDR3 calculates it as tQH=tHP- tQHS .
tQHS tells that if the data is late, how late it can be relative to the
strobe edge. tQHS is an output timing spec of the memory chips, which tries
to drive DQ and DQS as edge-aligned outputs.
Then DDR3 mixes it up with the half clock period. I never understood why it
was necessary. The DDR3 specs/datasheets say tHP=min(tCL,tCH) so it accounts
for the DCD as well.
regards,
Istvan Nagy
Bluechip Tech
-----Original Message-----
From: John Ellis
Sent: Thursday, January 27, 2011 4:15 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] DDR3 tQH spec.
Hello all,
I'm looking for some background on the development of the JEDEC requirement
for tQH (output hold) for DDR3
DDR3 specifies tQH =0.38 x tCK(avg). Was the 0.38 value selected to include
the impact of duty cycle distortion on the data valid window, or must I
still account for DCD in the timing budget?
DDR2 does not specify tQH, rather it calculates it as tQH=tHP- tQHS where
tQHS is "Hold Skew Factor" and tHP is the clock half pulse width which
account for duty cycle distortion.
Thanks!
John Ellis
Sr. Staff R&D Engineer
Mixed Signals &
I/O Libraries Group
Synopsys, Inc.
email: jellis@xxxxxxxxxxxx
Phone: 508.263.8194
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List technical documents are available at:
http://www.si-list.net
List archives are viewable at:
//www.freelists.org/archives/si-list
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List technical documents are available at:
http://www.si-list.net
List archives are viewable at:
//www.freelists.org/archives/si-list
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List technical documents are available at:
http://www.si-list.net
List archives are viewable at:
//www.freelists.org/archives/si-list
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
Other related posts:
