[SI-LIST] Re: PLL Jitter contribution in DDR3 system timing budget
- From: sreekanth soman <sreekanths18@xxxxxxxxx>
- To: sanjayg212@xxxxxxxxx
- Date: Mon, 12 Nov 2012 12:34:29 +0530
Sanjay,
Both the PLL jitter and the clock distribution (DCD) affects the hold
timing. This is the same for READ and WRITE timing as different clock edges
are used for hold.
On 9 November 2012 07:47, Sanjay G <sanjayg212@xxxxxxxxx> wrote:
> Hi Feng
> do you mean that no need to consider PLL jitter in write cycle, it should
> be considered only in read?
> thanks
>
>
> ________________________________
> From: å´æ« Feng Wu <wufengthu@xxxxxxx>
> To: wufengthu@xxxxxxx
> Cc: sanjayg212@xxxxxxxxx; "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
> Sent: Wednesday, November 7, 2012 2:33 PM
> Subject: [SI-LIST] Re: PLL Jitter contribution in DDR3 system timing budget
>
> Hi Sanjay
> If you are looking at the on-chip memory controller design, the jitter
> will impact most of the timing parameter. for example, it will impact the
> output skew and input setup/hold requirement. (at least in our chip, it is
> the case. I can't confirm it is always correct).
>
> If you are looking at the board level design, in Jedec spec, there is a
> chapter related with Jitter. It shows us which parameter is impacted by
> jitter.
> I would recommend you to pay more attention to memory read command. To get
> the accurate output window at memory pin, you need to manually subtract the
> clock jitter. Of course, clock jitter itself should fulfill the
> requirement of DDR3 chip.
> Thanks
> Feng
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Regards,
Sreekanth
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