[SI-LIST] Re: PLL Jitter contribution in DDR3 system timing budget
- From: 吴枫 Feng Wu <wufengthu@xxxxxxx>
- To: wufengthu@xxxxxxx
- Date: Wed, 7 Nov 2012 14:33:44 +0800 (CST)
Hi Sanjay
If you are looking at the on-chip memory controller design, the jitter will
impact most of the timing parameter. for example, it will impact the output
skew and input setup/hold requirement. (at least in our chip, it is the case. I
can't confirm it is always correct).
If you are looking at the board level design, in Jedec spec, there is a chapter
related with Jitter. It shows us which parameter is impacted by jitter.
I would recommend you to pay more attention to memory read command. To get the
accurate output window at memory pin, you need to manually subtract the clock
jitter. Of course, clock jitter itself should fulfill the requirement of DDR3
chip.
Thanks
Feng
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