[SI-LIST] Re: PDN question
- From: "Rick Brooks (ricbrook)" <ricbrook@xxxxxxxxx>
- To: "Joel Brown" <joel@xxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Thu, 20 Aug 2009 14:15:36 -0700
If a number of transistors switch low to high at the same time, then PDN
resonances can have a big impact.
You can also have data patterns at sub harmonics of the clock.
So it's a concern, unless you know about the limits of what can be
switching.
If, for example, you have a circuit that only draws current for 1 us
every 1 sec, then you do not need flat |Z| in the PDN, but you will need
to below a certain |Z| from below 1MHz to some upper limit.
It's hard to make sweeping conclusions about such a general case topic;
first state you application.
In the past, a flat PDN would handle general case chip power where the
average power/current is known, but any data pattern is possible.
thanks,
- Rick
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Joel Brown
Sent: Thursday, August 20, 2009 1:17 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] PDN question
Is it really necessary to have a PDN with impedance flat or below a
target
over a wide range of frequencies?
If a resonance occurs is it really a problem if there are no switching
currents at that frequency?
I am assuming that switching frequencies are a function of the clock
frequencies in the system.
Thanks - Joel
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