[SI-LIST] Re: PDN question

  • From: "Patrick G. Andre" <pat@xxxxxxxxxxxxxxxxxxx>
  • To: "'Patrick G. Andre'" <pat@xxxxxxxxxxxxxxxxxxx>, "'Lynne D. Green'" <lgreen22@xxxxxxxxxxxxxx>, "'Daniel Paradis \(paradid\)'" <paradid@xxxxxxxxx>, "'Si-List'" <si-list@xxxxxxxxxxxxx>
  • Date: Mon, 24 Aug 2009 09:42:02 -0700

Okay everyone: try http://andreconsulting.com/Circuit%20Board%20Work.pdf 

The hyperlink got unglued...

 - Patrick


-----Original Message-----
From: Patrick G. Andre [mailto:pat@xxxxxxxxxxxxxxxxxxx] 
Sent: Monday, August 24, 2009 9:20 AM
To: 'Lynne D. Green'; 'Daniel Paradis (paradid)'; 'Si-List'
Subject: RE: [SI-LIST] Re: PDN question

Many people were not able to receive the JPG files I sent.

Here is a clean copy of the report I generated.  It is significantly edited,
so it might seem somewhat confusing.  I am sorry for that.  Also, I have
learned a great deal since these days, including not to place high frequency
generators between connectors, for all the obvious reasons.

Here is the report: http://andreconsulting.com/Circuit Board Work.pdf -
again, please forgive all the "deleted" sections.

 - Patrick


-----Original Message-----
From: Lynne D. Green [mailto:lgreen22@xxxxxxxxxxxxxx] 
Sent: Friday, August 21, 2009 12:24 PM
To: Daniel Paradis (paradid); Si-List
Cc: help@xxxxxxxxxxxxxxxxxxx
Subject: Re: [SI-LIST] Re: PDN question

All,

The mentioned example was encountered by Pat Andre 
(http://www.andreconsulting.com/index.html), who described it as follows:

PDN formed a single loop around the outside edge of the board.
"Low cost" standard chip had fast edge.
EMI testing was done with board horizontal, so only edge emissions were 
actually tested.
Board was mounted vertical when system was installed in store.
FCC showed up the day system was turned on (day before opening store).
FCC shut their system down until fixed.
Fix was to run power and ground along the same edge of the PCB, removing 
the large loop area.
Fortunately, this could be done with a jumper rather than a respin.

Just an example of a low-clock system can have high-frequency PDN issues 
due to I/O edge rates.

Cheers,
Lynne


Daniel Paradis (paradid) wrote:
> I have never seen a before and after radiated emission test result with
> improvement due to corrected PDN design.
>
> Does anybody have some radiated emission results, at 3m or 10m in a real
> chamber, that would show a passing scan after a corrected PDN and
> failing scan with wrong PDN design?
>
>
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
> On Behalf Of Lynne D. Green
> Sent: Thursday, August 20, 2009 5:11 PM
> To: Joel Brown
> Cc: Si-List
> Subject: [SI-LIST] Re: PDN question
>
> Hi, Joel,
>
> The bad news: Yes, very high frequency components exist in signals.  The
>
> good news: Engineering skills (and EDA tools) can help identify risk.
>
> Several frequencies of interest, which are independent of clock rate:
> * I/O driver switching freq components
> * timing of I/O switching (time offsets between I/O)
> * ringing due to both real and parasitic R, L, C
> * transmission line reflections
>
> Some of these frequencies can easily be tens or hundreds (or more) times
>
> higher than the clock rate.  As an (admittedly extreme, but real) 
> example, there was one board where the clock was in the milli-Hz range, 
> and a PDN problem caused FCC violations in the Mega-Hz range.
>
> Happy designing!
>
> Cheers,
> Lynne
>
>
> "IBIS training when you need it, where you need it."
>
> Dr. Lynne Green
> Green Streak Programs
> http://www.greenstreakprograms.com
> 425-788-0412
> lgreen22@xxxxxxxxxxxxxx
>
>
>
>
>
> Joel Brown wrote:
>   
>> Is it really necessary to have a PDN with impedance flat or below a
>>     
> target
>   
>> over a wide range of frequencies?
>> If a resonance occurs is it really a problem if there are no switching
>> currents at that frequency?
>>
>> I am assuming that switching frequencies are a function of the clock
>> frequencies in the system.
>>
>>  
>>
>> Thanks - Joel
>>
>>   
>>     


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