[SI-LIST] Re: PCIe Gen2 coupling caps
- From: Jory McKinley <jory_mckinley@xxxxxxxxx>
- To: "ferhatyaldiz@xxxxxxxxx" <ferhatyaldiz@xxxxxxxxx>, "lakshminarayanans@xxxxxxx" <lakshminarayanans@xxxxxxx>
- Date: Sat, 7 Dec 2013 12:01:37 -0800 (PST)
Hello Joel,
If you do not have access to a 3D then how about a board tool like
SIWave/PowerSI? For PCIe Gen 2 you can live with a 2.5D with z-direction 3D
FFM engine by removing the capacitor and shorting the connections. Do this for
both the cutout and the non-cutout cases. Check the impedance discontinuity,
insertion loss, return loss, and eye metrics. Also check for coupling and mode
conversion to nearby structures for the cases this should give you information
as to how well contained the currents are through the void. The 3D solvers
allow for detailed capacitor modeling and inclusion into your channel and
showing through 3D animation all current paths and modes but below 7.5Ghz or so
you should be ok with short that represents your capacitor dimensions.
-Jory
On Saturday, December 7, 2013 5:53 AM, Ferhat Yaldiz <ferhatyaldiz@xxxxxxxxx>
wrote:
Hi Joel,
Below documents will be very helpful for cutout areas in GND planes for
PCIe signals.
http://www.altera.co.jp/literature/an/an530.pdf
http://www.simberian.com/AppNotes/AC_CouplingCapacitors_2008_04.pdf
and you can follow older post :
//www.freelists.org/post/si-list/reference-plane-cutout-under-DC-blocking-capacitor-pads
Regards,
Ferhat Yaldiz
2013/12/6 Lakshmi Narayanan Sowrirajan, ERS-HCLTech <
lakshminarayanans@xxxxxxx>
> Hi Joel,
>
> It will really help in your signal quality .
> You may have to use 3D modeling tools (eg HFSS) to models this cutout in
> the GND plane and extract the s parameter to use in your simulations.
>
> Note: I hope HyperLynx also have the capability in its latest version for
> 3D modeling.
>
> Thanks & Regards
> Lakshminarayanan. S
>
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
> On Behalf Of Joel Brown
> Sent: Friday, December 06, 2013 11:48 AM
> To: SI-List
> Subject: [SI-LIST] PCIe Gen2 coupling caps
>
> Is it necessary or desirable to cutout the reference plane under the
> coupling caps for PCIe Gen2?
> If I want to include a model for the capacitor with or without the cutouts
> in a Hspice simulation what would be the best way to do this? I likely will
> be using 0201 size caps.
> Thanks
>
>
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