[SI-LIST] Re: PCIe Gen2 coupling caps
- From: "Lee " <leeritchey@xxxxxxxxxxxxx>
- To: <Megan.Wiskur@xxxxxxxxxxxxxx>, <joel@xxxxxxxxxx>, "SI-List" <si-list@xxxxxxxxxxxxx>
- Date: Tue, 10 Dec 2013 12:17:37 -0800
It is far more important to manage the capacitance of the vias used to
connect to the capacitors.
-----Original Message-----
From: Megan Wiskur
Sent: Tuesday, December 10, 2013 6:13 AM
To: leeritchey@xxxxxxxxxxxxx ; joel@xxxxxxxxxx ; SI-List
Subject: [SI-LIST] Re: PCIe Gen2 coupling caps
I agree, based on testcards we've made. Seems that the overall impedance
discontinuity should be kept as short as possible.
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Lee
Sent: Monday, December 09, 2013 3:28 PM
To: joel@xxxxxxxxxx; SI-List
Subject: [SI-LIST] Re: PCIe Gen2 coupling caps
No, it does not make a significant difference. Based on measured data on
real test PCBs. Spend you time on bigger issues.
-----Original Message-----
From: Joel Brown
Sent: Friday, December 06, 2013 11:48 AM
To: SI-List
Subject: [SI-LIST] PCIe Gen2 coupling caps
Is it necessary or desirable to cutout the reference plane under the
coupling caps for PCIe Gen2?
If I want to include a model for the capacitor with or without the cutouts
in a Hspice simulation what would be the best way to do this? I likely will
be using 0201 size caps.
Thanks
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