[SI-LIST] Re: PCI/PCIX minimum lenghts?
- From: "Mcgrath, Christopher" <christopher.mcgrath@xxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Thu, 10 Nov 2005 10:54:32 -0700
In short, the biggest problem with short point-to-point PCI applications
is the ringing- both from a signal quality side as well as the tolerance
of the receivers. One thing to keep in mind and check out that was not
mentioned yet is that PCI and PCIX do not clearly define tolerances for
AC overshoot/undershoot (although PCIX 2.0 does a better job with this),
so you may be surprised at the variance between how chip vendors
interpret the PCI specification on this topic. The PCI spec defines a
DC Vmax and Vmin, but not a condition for transient overshoot and
undershoot.
Summary: Point-to-point (even on longer traces) topologies with PCI-X
capable drivers can benefit from series resistors on each end of the
transmission line. I recommend dialing the value through simulation,
but I agree with Ed that the 25 ohm range should be in the ballpark.
Check your AC overshoot/undershoot and, if it is in excess of the PCI DC
specification, you may want to start talking to your PCI chip vendor.
-Chris
>-----Original Message-----
>From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx] On
>Behalf Of Dr. Edward P. Sayre
>Sent: Thursday, November 10, 2005 9:59 AM
>To: af@xxxxxx; si-list@xxxxxxxxxxxxx
>Subject: [SI-LIST] Re: PCI/PCIX minimum lenghts?
>
>Anders:
>
>Try 10 - 25 ohm series resistors on the traces if you find the short
link
>causes ringing. It will slow everything down and make the bus appear
>longer than it really is.
>
>ed
>=3D=3D
>At 12:21 PM 11/10/2005 +0100, Anders Frederiksen wrote:
>>Hi people =3D),
>>
>>I'm working on a board with a PCI-X (66Mhz) and a PCI (33Mhz) bus.
Both
>>busses are
>>point to point embedded busses. According to specs the minimum length
of a
>>PCI bus
>>seems to be ~95mm. Given the number of signals and the fact that the
>>optimal length
>>is ~3cm I understand the PCB designers frustrations! Thus I'd like to
>>relax the
>>minimum length constraint...
>>
>>Has anyone looked into "short PCI busses"? I see two possible issues:
1.
>>Bus being
>>too short for transmission line theory to apply. Possibly affecting
signal
>>levels.
>>2. Timing for host reads: The data will arrive earlier than "expected"
due
>>to the
>>shorter clock (out) and data (return) propagation.
>>
>>My googling provided no usable results. Perhaps you guys would have a
hint
>>or two?
>>
>>Cheers,
>>Anders
>>
>>
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>
>
>
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