[SI-LIST] Re: PCB layer stackup
- From: "Andrew Ingraham" <a.ingraham@xxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Tue, 16 Jan 2007 11:13:02 -0500
> Many times you will get lower emissions from a product by routing your
> clock traces on the outer layers (assuming they are over a ground
> plane). I first saw this in an IEEE EMC conference paper and experience
> bears it out.
Interesting. This seems counter-intuitive. Why does this happen?
Andy
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