[SI-LIST] Re: Opinions wanted on Signal Integrity analysis tools
- From: Dorin Oprea <dorin.oprea@xxxxxxxxxxx>
- To: kalevi@xxxxxxxxxx
- Date: Tue, 31 Jan 2006 08:45:47 -0500
Kai:
Do you speak about the PCB SI Channel Analysis tool?
If so, I would like to get some more detail on:
1) Is the via model created based on 3D EM tool?
Can the user create his own 3D geometry and generate the corresponding model?
Or, is the model created on close form formulae?
2) Is the tool suitable for Gbps interconnect design work in the sense that each
model is direct accessible and thus, the designer can change or even
parameterize the circuit elements and in this way optimize the via geometry, the
routing through the pin field, and the stack up.
3) Or, is the tool mainly a layout verification in the sense that the input in
to the SI simulation tool is based upon the layout database?
Best regards,
Dorin
Kai Keskinen wrote:
> Tom:
>
> You need a tool that has a 3D field solver. If you are doing multi-gigabit
> design, I would recomend Cadence Allegro PCB SI 630 (note I said 630) which
> has a field solver that can deal with coupled vias and generate multiport
> touchstone format S parameter files for vias, transmission lines, etc. You
> can simulate in APCBSI if you have an IBIS model or you can link to HSPICE
> or move your S parameter files to HSPICE. HSPICE is also helpful since many
> of the MGHz silicon models are only available in HSPICE encrypted format.
> HSPICE recently allowed time domain simulation with frequency domain S
> parameter files increasing its usefulness by an order of magnitude for this
> kind of work. This combination of tools is fairly pricy but no 3D field
> solver is cheap. HFSS is an other candidate but you still need a simulation
> engine like HSPICE for the encrypted models. HSPICE also has a pretty good
> 2D field solver for transmission lines and cable cross-sections. The other
> advantage Cadence will have is you can load an entire board file (as long as
> it is in Allegro or can be translated) and get the transmission lines, pads,
> etc. into your S parameter files for a transmission path. The other
> advantage with Cadence is that the learning curve for the MGHz is fairly
> shallow unlike tools like HFSS where you can spend a long time getting to
> know how to run it properly.
>
> I'm sure you will get half a dozen other solutions and the sales folks from
> each company will do their best to tell you why their tool is the right one
> for you.
>
> In selling your need for simulation tools to your management, estimate how
> much it costs to do a board respin in direct costs and in in-direct costs
> such as people sitting around waiting, lost sales opportunities, lost market
> window, etc. One less respin pays for the cost of the tools and 2 less puts
> money in the bank.
>
> Good luck.
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of tom_cip_11551
> Sent: Monday, January 30, 2006 4:58 PM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Opinions wanted on Signal Integrity analysis tools
>
> Hi,
>
> At present, I work for a small company that does gigabit design,
> pretty much by experiment. If we do not make our return loss
> specification, we take some copper away from the ground layer, or do
> something else, until we do make it. We may turn the board a few
> times but that is the way it goes.
>
> I have done a number evauations of programs that do EM analysis,
> such as AWR Microwave Office, CST Microwave Studio and Sonnet EM
> Suite.
>
> I would like to know if there is an opinion in the group concerning
> any other programs that are generally used. For example, I have read
> some data about Cadence Specctraquest. Specctraquest, however,
> appears to be more model based (pspice) than EM based.
>
> Before I make a proposal to management for capital equipment, I
> would like to get more opinions for the SI group.
>
> The main challenge that we have, is the mating of high speed
> connectors to the PCB. Sometimes we can get spice models of the
> connector, by itself, but that does not do us much good concerning
> the mating interface of the PCB pad to the connector pin.
>
> Thank You
> Tom
>
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