[SI-LIST] Re: Memory Signal Integrity
- From: steve weir <weirsi@xxxxxxxxxx>
- To: kenny_frohlich@xxxxxxxxx,si-list@xxxxxxxxxxxxx
- Date: Thu, 21 Sep 2006 05:02:41 -0700
Kenny, you will always need to know the relationship between data and
clock at the sampler. So no matter where you look at the clock you
will need to normalize it to the die. SDR SDRAM has a lot of slop,
so you can tolerate errors in the analysis like looking at the clock
a moderate distance away without correction.
Steve.
At 09:12 PM 9/20/2006, Kenny Frohlich wrote:
>Hi Expert,
> I have a question on memory signal integrity:
> For memory write cycle, both data and clock signals are probed at
> the memory device (SDRAM).
> For memory read cycle, data signal is probed at the CPU (memory
> controller). But where should I probe the clock signal - at the
> CPU (source) or at the memory device (destination)? The clock
> signal is much cleaner at the memory device.
>
> Thanks,
> Kenny
>
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